DS26518GN+ Maxim Integrated Products, DS26518GN+ Datasheet - Page 56

• Manufacturer Part Number: DS26518GN+
• Description: IC TXRX T1/E1/J1 8PORT 256-CSBGA
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS26518GN+

• Number Of Drivers/receivers: 8/8
• Protocol: T1/E1/J1
• Voltage - Supply: 3.135 V ~ 3.465 V
• Mounting Type: Surface Mount
• Package / Case: 256-CSBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS26518 8-Port T1/E1/J1 Transceiver
9.9.4.2 Receive-Signaling Operation
There are two methods to access receive-signaling data and provide transmit-signaling data: processor based (i.e.,
software based) or hardware based. Processor-based refers to access through the transmit- and receive-signaling
registers, RS1–RS16. Hardware based refers to the RSIGn pin. Both methods can be used simultaneously.
9.9.4.2.1 Processor-Based Receive Signaling
Signaling information is sampled from the receive data stream and copied into the Receive-Signaling Registers,
RS1–RS16. The signaling information in these registers is always updated on multiframe boundaries. This function
is always enabled.
9.9.4.2.2 Change of State
To avoid constant monitoring of the receive-signaling registers, the DS26518 can be programmed to alert the host
when any specific channel or channels undergo a change of their signaling state. RSCSE1–4 are used to select
which channels can cause a change of state indication. The change of state is indicated in Receive Latched Status
Register 4 (RLS4.3). If signaling integration is enabled, the new signaling state must be constant for three
multiframes before a change of state indication is indicated. The user can enable the INTB pin to toggle low upon
detection of a change in signaling by setting the interrupt mask bit RIM4.3. The signaling integration mode is global
and cannot be enabled on a channel-by-channel basis.
The user can identity which channels have undergone a signaling change of state by reading the Receive-
Signaling Status Registers (RSS1–4) . The information from these registers will tell the user which RSx register to
read for the new signaling data. All changes are indicated in the RSS1–4 registers regardless of the RSCSE1–4
registers.
9.9.4.2.3 Hardware-Based Receive Signaling
In hardware-based signaling the signaling data is can be obtained from the RSERn pin or the RSIGn pin. RSIGn is
a signaling PCM stream output on a channel by channel basis from the signaling buffer. The T1 robbed bit or E1
TS16 signaling data is still present in the original data stream at RSERn. The signaling buffer provides signaling
data to the RSIGn pin and also allows signaling data to be reinserted into the original data stream in a different
alignment that is determined by a multiframe signal from the RSYNCn pin. In this mode, the receive elastic store
may be enabled or disabled. If the receive elastic store is enabled, then the backplane clock (RSYSCLKn) can be
either 1.544MHz or 2.048MHz. In the ESF framing mode, the ABCD signaling bits are output on RSIGn in the lower
nibble of each channel. The RSIGn data is updated once a multiframe (3ms for T1 ESF, 1.5ms for T1 D4, 2ms for
E1 CAS) unless a signaling freeze is in effect. In the D4 framing mode, the AB signaling bits are output twice on
RSIGn in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as bits 7 and 8, respectively,
in each channel.
9.9.4.2.4 Receive-Signaling Reinsertion at RSERn
In this mode, the user will provide a multiframe sync at the RSYNCn pin and the signaling data will be reinserted
based on this alignment. In T1 mode, this results in two copies of the signaling data in the RSERn data stream. The
original signaling data based on the Fs/ESF frame positions and the realigned data based on the user supplied
multiframe sync applied at RSYNCn. In voice channels this extra copy of signaling data is of little consequence.
Reinsertion can be avoided in data channels since this feature is activated on a per-channel basis. For reinsertion,
the elastic store must be enabled and for T1, the backplane clock can be either 1.544MHz or 2.048MHz. E1
signaling information cannot be reinserted into a 1.544MHz backplane.
Signaling reinsertion mode is enabled, on a per-channel basis by setting the receive-signaling reinsertion channel
select bit high in the RSI1–4 register. The channels that are to have signaling reinserted are selected by writing to
the RSI1–4 registers. In E1 mode, the user will generally select all channels or none for reinsertion.
9.9.4.2.5 Force Receive-Signaling All Ones
In T1 mode, the user can on a per-channel basis force the robbed-bit signaling bit positions to a one. This is done
by using the Receive-Signaling All-Ones Insertion Registers (T1RSAOI1–3). The user sets the channel select bit in
the T1RSAOI1–3 registers to select the channels that are to have the signaling forced to one.
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