74HC390D,652

Manufacturer Part Number74HC390D,652
DescriptionDUAL DECADE RIPPLE COUNTER
ManufacturerPhilips Semiconductors
74HC390D,652 datasheet
 


Specifications of 74HC390D,652

Circuit TypeHigh Speed, Low-Power Schottky, Silicon GateFunction Type4-Bits
Logic FunctionCounterLogic TypeCMOS
Number Of CircuitsDualPackage TypeSO-16
Special FeaturesDecade, RippleTemperature, Operating, Range-40 to +125 °C
Voltage, Supply4.5 VLead Free Status / Rohs StatusRoHS Compliant part Electrostatic Device
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Philips Semiconductors
Dual decade ripple counter
FEATURES
Two BCD decade or bi-quinary counters
One package can be configured to divide-by-2, 4, 5, 10,
20, 25, 50 or 100
Two master reset inputs to clear each decade counter
individually
Output capability: standard
I
category: MSI
CC
GENERAL DESCRIPTION
The 74HC/HCT390 are high-speed Si-gate CMOS devices
and are pin compatible with low power Schottky TTL
(LSTTL). They are specified in compliance with JEDEC
standard no. 7A.
The 74HC/HCT390 are dual 4-bit decade ripple counters
divided into four separately clocked sections. The counters
have two divide-by-2 sections and two divide-by-5
sections. These sections are normally used in a BCD
QUICK REFERENCE DATA
GND = 0 V; T
= 25 C; t
= t
= 6 ns
amb
r
f
SYMBOL
PARAMETER
t
/ t
propagation delay
PHL
PLH
nCP
to nQ
0
0
nCP
to nQ
1
1
nCP
to nQ
1
2
nCP
to nQ
1
3
nMR to Q
n
f
maximum clock frequency nCP
max
C
input capacitance
I
C
power dissipation capacitance per counter
PD
Notes
1. C
is used to determine the dynamic power dissipation (P
PD
2
P
= C
V
f
(C
D
PD
CC
i
f
= input frequency in MHz
i
f
= output frequency in MHz
o
2
(C
V
f
) = sum of outputs
L
CC
o
C
= output load capacitance in pF
L
V
= supply voltage in V
CC
2. For HC the condition is V
= GND to V
I
For HCT the condition is V
= GND to V
I
decade or bi-quinary configuration, since they share a
common master reset input (nMR). If the two master reset
inputs (1MR and 2MR) are used to simultaneously clear all
8 bits of the counter, a number of counting configurations
are possible within one package. The separate clocks
(nCP
and nCP
0
frequency division applications of divide-by-2, 4, 5, 10, 20,
25, 50 or 100.
Each section is triggered by the HIGH-to-LOW transition of
the clock inputs (nCP
operation, the nQ
of, the divide-by-5 section. For bi-quinary decade
operation, the nQ
and nQ
0
The master reset inputs (1MR and 2MR) are active HIGH
asynchronous inputs to each decade counter which
operates on the portion of the counter identified by the “1”
and “2” prefixes in the pin configuration. A HIGH level on
the nMR input overrides the clocks and sets the four
outputs LOW.
C
= 15 pF; V
L
, nCP
0
1
notes 1 and 2
in W):
D
2
V
f
) where:
L
CC
o
CC
1.5 V
CC
2
Product specification
74HC/HCT390
) of each section allow ripple counter or
1
and nCP
). For BCD decade
0
1
output is connected to the nCP
0
output is connected to the nCP
3
becomes the decade output.
TYPICAL
CONDITIONS
HC
HCT
= 5 V
CC
14
18
15
19
23
26
15
19
16
18
66
61
3.5
3.5
20
21
input
1
input
0
UNIT
ns
ns
ns
ns
ns
MHz
pF
pF

74HC390D,652 Summary of contents

  • Page 1

    ... Philips Semiconductors Dual decade ripple counter FEATURES Two BCD decade or bi-quinary counters One package can be configured to divide-by- 10, 20, 25 100 Two master reset inputs to clear each decade counter individually Output capability: standard I category: MSI CC GENERAL DESCRIPTION The 74HC/HCT390 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL) ...

  • Page 2

    ... Philips Semiconductors Dual decade ripple counter DC CHARACTERISTICS FOR 74HC For the DC characteristics see “74HC/HCT/HCU/HCMOS Logic Family Specifications” Output capability: standard I category: MSI CC AC CHARACTERISTICS FOR 74HC GND = ns SYMBOL PARAMETER propagation delay PHL PLH nCP propagation delay PHL PLH nCP to nQ ...