ATA6622-PGPW Atmel, ATA6622-PGPW Datasheet - Page 15

• Manufacturer Part Number: ATA6622-PGPW
• Description: TXRX LIN BUS REG WATCHDOG 20-QFN
• Manufacturer: Atmel
• Type: Transceiverr

Specifications of ATA6622-PGPW

• Number Of Drivers/receivers: 1/1
• Protocol: LIN
• Voltage - Supply: 5 V ~ 27 V
• Mounting Type: Surface Mount
• Package / Case: 20-QFN Exposed Pad
• Processor Series: ATA6x
• Core: AVR8
• Data Bus Width: 8 bit
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6. Watchdog
6.1
4986J–AUTO–03/11
Typical Timing Sequence with R
The watchdog anticipates a trigger signal from the microcontroller at the NTRIG (negative
edge) input within a time window of T
t
NRES. The timing basis of the watchdog is provided by the internal oscillator. Its time period,
T
During Silent or Sleep Mode the watchdog is switched off to reduce current consumption.
The minimum time for the first watchdog pulse is required after the undervoltage reset at
NRES disappears. It is defined as lead time t
lead time t
The trigger signal T
R
For example, with an external resistor of R
watchdog are as follows:
t
t
t
t
t
t
After ramping up the battery voltage, the 3.3V/5V regulator is switched on. The reset output
NRES stays low for the time t
waits for the trigger sequence from the microcontroller. The lead time, t
is t
trigger pulse NTRIG occurs during this time, the time t
occurs during the time t
t
nal from the microcontroller is anticipated within the time frame of t
triggering from glitches, the trigger pulse must be longer than t
serves to restart the watchdog sequence. If the triggering signal fails in this open window t
the NRES output will be drawn to ground. A triggering signal during the closed window t
immediately switches NRES to low.
trigmin
osc
OSC
d
1
2
nres
d
osc
WD_OSC
= 7895
= 1053
= 1105
= 155ms. The times t
d
= 0.405
, is adjustable via the external resistor R
= constant = 4ms
= 155ms. In this time, the first watchdog pulse from the microcontroller is required. If the
= 19.6µs due to 51k
> 200ns. If a triggering signal is not received, a reset signal will be generated at output
.
d
starts with the negative edge of the RXD output.
19.6µs = 20.6ms
19.6µs = 155ms
19.6µs = 21.6ms
R
WD_OSC
WD_OSC
wd
– 0.0004
d
1
is adjustable between 20ms and 64ms using the external resistor
, a watchdog reset with t
and t
Atmel ATA6622/ATA6624/ATA6626
= 51k
2
reset
have a fixed relationship between each other. A triggering sig-
(typically 4ms), then it switches to high, and the watchdog
(R
WD_OSC
wd
. The trigger signal must exceed a minimum time
WD_OSC
wd_osc
)
2
d
. After wake up from Sleep or Silent Mode, the
(R
NRES
WD_OSC
(34k to 120k ).
= 51k ±1%, the typical parameters of the
= 4ms will reset the microcontroller after
1
starts immediately. If no trigger signal
in k ; t
osc
TRIG,min
in µs)
2
= 21.6ms. To avoid false
d
, follows the reset and
> 200ns. This slope
15
2
1
,