PIC16F627-04/SO Microchip Technology Inc., PIC16F627-04/SO Datasheet - Page 49

• Manufacturer Part Number: PIC16F627-04/SO
• Description: 18 PIN, 1.75 KB FLASH, 224 RAM, 16 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F627-04/SO

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 128 Bytes
• Input Output: 16
• Interface: SCI/USART
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 18-pin SOIC
• Programmable Memory: 1.75K Bytes
• Ram Size: 224 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

7.1
Timer mode is selected by clearing the TMR1CS
(T1CON<1>) bit. In this mode, the input clock to the
timer is F
(T1CON<2>) has no effect since the internal clock is
always in sync.
7.2
Counter mode is selected by setting bit TMR1CS. In
this mode the timer increments on every rising edge of
clock input on pin RB7/T1OSI when bit T1OSCEN is
set or pin RB6/T1OSO/T1CKI when bit T1OSCEN is
cleared.
If T1SYNC is cleared, then the external clock input is
synchronized with internal phase clocks. The synchro-
nization is done after the prescaler stage. The
prescaler stage is an asynchronous ripple-counter.
In this configuration, during SLEEP mode, Timer1 will
not increment even if the external clock is present,
since the synchronization circuit is shut off. The
prescaler however will continue to increment.
FIGURE 7-1:
 2003 Microchip Technology Inc.
Note
RB6/T1OSO/T1CKI
RB7/T1OSI
1:
Timer1 Operation in Timer Mode
Timer1 Operation in Synchronized
Counter Mode
OSC
Set flag bit
TMR1IF on
Overflow
When the T1OSCEN bit is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
/4. The synchronize control bit T1SYNC
TIMER1 BLOCK DIAGRAM
TMR1H
T1OSC
TMR1
TMR1L
Oscillator(1)
Enable
T1OSCEN
Preliminary
Internal
Clock
F
OSC
/4
TMR1ON
TMR1CS
1
0
7.2.1
When an external clock input is used for Timer1 in
Synchronized Counter mode, it must meet certain
requirements. The external clock requirement is due to
internal phase clock (Tosc) synchronization. Also, there
is a delay in the actual incrementing of TMR1 after
synchronization.
When the prescaler is 1:1, the external clock input is
the same as the prescaler output. The synchronization
of T1CKI with the internal phase clocks is accom-
plished by sampling the prescaler output on the Q2 and
Q4 cycles of the internal phase clocks. Therefore, it is
necessary for T1CKI to be high for at least 2Tosc (and
a small RC delay of 20 ns) and low for at least 2Tosc
(and a small RC delay of 20 ns). Refer to the appropri-
ate electrical specifications, parameters 45, 46, and 47.
When a prescaler other than 1:1 is used, the external
clock input is divided by the asynchronous ripple-
counter type prescaler so that the prescaler output is
symmetrical. In order for the external clock to meet the
sampling requirement, the ripple-counter must be
taken into account. Therefore, it is necessary for T1CKI
to have a period of at least 4Tosc (and a small RC delay
of 40 ns) divided by the prescaler value. The only
requirement on T1CKI high and low time is that they do
not violate the minimum pulse width requirements of 10
ns). Refer to the appropriate electrical specifications,
parameters 40, 42, 45, 46, and 47.
T1CKPS1:T1CKPS0
T1SYNC
Prescaler
1, 2, 4, 8
EXTERNAL CLOCK INPUT TIMING
FOR SYNCHRONIZED COUNTER
MODE
0
1
2
Synchronized
PIC16F62X
Clock Input
Synchronize
SLEEP Input
det
DS40300C-page 47