PIC16F72-I/SO Microchip Technology Inc., PIC16F72-I/SO Datasheet - Page 41

• Manufacturer Part Number: PIC16F72-I/SO
• Description: 28 PIN, 3.5 KB FLASH, 128 RAM, 22 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F72-I/SO

• A/d Inputs: 5-Channel, 8-Bit
• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 22
• Interface: I2C/SPI
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 28-pin SOIC
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 2-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

8.2 Compare Mode
In Compare mode, the 16-bit CCPR1 register value is
constantly compared against the TMR1 register pair
value. When a match occurs, the RC2/CCP1 pin is:
• Driven High
• Driven Low
• Remains Unchanged
The action on the pin is based on the value of control
bits CCP1M3:CCP1M0 (CCP1CON<3:0>). At the
same time, interrupt flag bit CCP1IF is set.
The output may become inverted when the mode of the
module is changed from Compare/Clear on Match
(CCPxM<3:0> = ‘1001’) to Compare/Set on Match
(CCPxM<3:0> = ‘1000’). This may occur as a result of
any operation that selectively clears bit CCPxM0, such
as a BCF instruction.
When this condition occurs, the output becomes
inverted when the instruction is executed. It will remain
inverted for all following Compare operations, until the
module is reset.
FIGURE 8-2:
 2002 Microchip Technology Inc.
RC2/CCP1
pin
Special event trigger will:
• RESET Timer1, but not set interrupt flag bit TMR1IF
• Set bit GO/DONE (ADCON0<2>) bit, which starts an A/D
(PIR1<0>)
conversion
Output Enable
TRISC<2>
Q
Special Event Trigger
R
S
CCP1CON<3:0>
Mode Select
Output
COMPARE MODE
OPERATION BLOCK
DIAGRAM
Logic
(PIR1<2>)
Set Flag bit CCP1IF
Match
CCPR1H CCPR1L
TMR1H
Comparator
TMR1L
8.2.1
The user must configure the RC2/CCP1 pin as an
output by clearing the TRISC<2> bit.
8.2.2
Timer1 must be running in Timer mode or Synchro-
nized Counter mode, if the CCP module is using the
compare feature. In Asynchronous Counter mode, the
compare operation may not work.
8.2.3
When generate software interrupt is chosen, the CCP1
pin is not affected. Only a CCP interrupt is generated (if
enabled).
8.2.4
In this mode, an internal hardware trigger is generated
that may be used to initiate an action.
The special event trigger output of CCP1 resets the
TMR1 register pair. This allows the CCPR1 register to
effectively be a 16-bit programmable period register for
Timer1.
The special trigger output of CCP1 resets the TMR1
register pair, and starts an A/D conversion (if the A/D
module is enabled).
Note:
Note:
Clearing the CCP1CON register will force
the RC2/CCP1 compare output latch to the
default low level. This is not the data latch.
The special event trigger from the CCP1
module will not set interrupt flag bit
TMR1IF (PIR1<0>).
CCP PIN CONFIGURATION
TIMER1 MODE SELECTION
SOFTWARE INTERRUPT MODE
SPECIAL EVENT TRIGGER
PIC16F72
DS39597B-page 39