ISPLSI1032E-100LTN Lattice, ISPLSI1032E-100LTN Datasheet

ISPLSI1032E-100LTN

Manufacturer Part Number

ISPLSI1032E-100LTN

Description

ISPLSI 1000E 6K GATES 128 MC 125MHZ EECMOS 5V 100TQFP

Manufacturer

Lattice

Datasheet

1.ISPLSI1032E-100LTN.pdf (9 pages)

Specifications of ISPLSI1032E-100LTN

Circuit Type

Fast

Current, Supply

190 mA

Logic Function

Programmable

Logic Type

CMOS

Package Type

TQFP-100

Special Features

High Density, High Speed, In-System Programmability

Temperature, Operating, Range

0 to +70 °C

Voltage, Supply

5.25 V

Lead Free Status / Rohs Status

RoHS Compliant part Electrostatic Device

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• HIGH DENSITY PROGRAMMABLE LOGIC

• HIGH PERFORMANCE E

• IN-SYSTEM PROGRAMMABLE

• OFFERS THE EASE OF USE AND FAST SYSTEM

1032e_09

to change without notice.

LATTICE SEMICONDUCTOR CORP

Features

— 6000 PLD Gates

— 64 I/O Pins, Eight Dedicated Inputs

— 192 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

—

— TTL Compatible Inputs and Outputs

— Electrically Erasable and Reprogrammable

— Non-Volatile

— 100% Tested at Time of Manufacture

— Unused Product Term Shutdown Saves Power

— In-System Programmable (ISP™) 5V Only

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Four Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

— Lead-Free Package Options

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

Machines, Address Decoders, etc.

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

max = 125 MHz Maximum Operating Frequency

pd = 7.5 ns Propagation Delay

CMOS

TECHNOLOGY

In-System Programmable High Density PLD

The ispLSI 1032E is a High Density Programmable Logic

Device containing 192 Registers, 64 Universal I/O pins,

eight Dedicated Input pins, four Dedicated Clock Input

pins and a Global Routing

provides complete interconnectivity between all of these

elements. The ispLSI 1032E device offers 5V non-vola-

tile in-system programmability of the logic, as well as the

interconnects to provide truly reconfigurable systems. A

functional superset of the ispLSI 1032 architecture, the

ispLSI 1032E device adds two new global output enable

pins.

The basic unit of logic on the ispLSI 1032E device is the

Generic Logic Block (GLB). The GLBs are labeled A0,

A1…D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 1032E device. Each GLB has 18 inputs, a pro-

grammable AND/OR/Exclusive OR array, and four outputs

which can be configured to be either combinatorial or

registered. Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any GLB on the device.

Functional Block Diagram

Description

D7 D6 D5 D4 D3 D2 D1 D0

B0 B1 B2 B3 B4 B5 B6 B7

Global Routing Pool (GRP)

Output Routing Pool

ispLSI

Logic

Array

D Q

Pool (GRP). The GRP

GLB

1032E

CLK

0139A(A1)-isp

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ISPLSI1032E-100LTN Summary of contents

Page 1

... Optimized Global Routing Pool Provides Global Interconnectivity — Lead-Free Package Options Copyright © 2006 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP ...

Page 2

Functional Block Diagram Figure 1. ispLSI 1032E Functional Block Diagram RESET Generic Logic Blocks (GLBs) I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O ...

Page 3

Absolute Maximum Ratings Supply Voltage V ...................................-0.5 to +7.0V cc Input Voltage Applied ........................ -2 Off-State Output Voltage Applied ..... -2 Storage Temperature ................................ -65 to 150°C Case Temp. with Power Applied .............. -55 to 125°C ...

Page 4

... Typical values are and T = 25° Maximum I varies widely with specific device configuration and operating frequency. Refer to the Power Consumption CC section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum Specifications ispLSI 1032E Figure 2. Test Load GND to 3 ...

Page 5

External Timing Parameters 4 TEST 2 # PARAMETER COND Data Propagation Delay, 4PT Bypass, ORP Bypass pd1 Data Propagation Delay, Worst Case Path pd2 Clock Frequency with Internal Feedback max (Int.) ...

Page 6

Internal Timing Parameters 2 PARAM. # Inputs t 22 I/O Register Bypass iobp t 23 I/O Latch Delay iolat t iosu 24 I/O Register Setup Time before Clock t 25 I/O Register Hold Time after Clock ioh t 26 I/O ...

Page 7

Internal Timing Parameters PARAM. # Outputs t 49 Output Buffer Delay Output Buffer Delay, Slew Limited Adder sl t oen 51 I/O Cell OE to Output Enabled t 52 I/O Cell OE to Output Disabled odis t ...

Page 8

Part Number Description ispLSI Device Family Device Number Speed f 125 = 125 MHz max f 100 = 100 MHz max MHz max MHz max MHz max ispLSI ...

Page 9

... INDUSTRIAL ORDERING NUMBER 15 ispLSI 1032E-70LJNI 15 ispLSI 1032E-70LTNI Previous Lattice release. Updated for lead-free package options. 17 PACKAGE Lead-Free 84-Pin PLCC Lead-Free 100-Pin TQFP Lead-Free 84-Pin PLCC Lead-Free 100-Pin TQFP Lead-Free 84-Pin PLCC Lead-Free 100-Pin TQFP PACKAGE Lead-Free ...

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