PIC16F636-I/P Microchip Technology Inc., PIC16F636-I/P Datasheet - Page 114

• Manufacturer Part Number: PIC16F636-I/P
• Description: 14 PIN, 3.5 KB FLASH, 128 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16F636-I/P

• Comparators: 2
• Cpu Speed: 5 MIPS
• Eeprom Memory: 256 Bytes
• Input Output: 12
• Memory Type: Flash
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 3.5K Bytes
• Ram Size: 128 Bytes
• Speed: 20 MHz
• Timers: 1-8-bit, 1-16-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC12F635/PIC16F636/639
12.1
The Configuration Word bits can be programmed (read
as ‘0’), or left unprogrammed (read as ‘1’) to select
various device configurations as shown in Register 12-1.
These bits are mapped in program memory location
2007h.
REGISTER 12-1:
DS41232B-page 112
bit 13
bit 13
bit 12
bit 11
bit 10
bit 9-8
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
U-1
—
WURE FCMEN
Configuration Word Bits
R/P-1
Unimplemented: Read as ‘1’
WURE: Wake-up Reset Enable bit
1 = Standard wake-up and continue enabled
0 = Wake-up and Reset enabled
FCMEN: Fail-Safe Clock Monitor Enable bit
1 = Fail-Safe Clock Monitor enabled
0 = Fail-Safe Clock Monitor disabled
IESO: Internal-External Switchover bit
1 = Internal External Switchover mode enabled
0 = Internal External Switchover mode disabled
BODEN<1:0>: Brown-out Detect Enable bits
11 = BOD enabled and SBODEN bit disabled
10 = BOD enabled while running and disabled in Sleep. SBODEN bit disabled.
01 = SBODEN in Register 2-6 controls BOD function
00 = BOD and SBODEN disabled
CPD: Code Protection Data bit
1 = Data memory is not protected
0 = Data memory is external read protected
CP: Code Protection bit
1 = Program memory is not code-protected
0 = Program memory is external read and write-protected
MCLRE: MCLR Pin Function Select bit
1 = MCLR pin is MCLR function and weak internal pull-up is enabled
0 = MCLR pin is alternate function, MCLR function is internally disabled
PWRTE: Power-up Timer Enable bit
1 = PWRT disabled
0 = PWRT enabled
WDTE: Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled and can be enabled using SWDTEN in Register 12-2
FOSC<2:0>: Oscillator Selection bits
000 = LP oscillator: Low power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT
001 = XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT
010 = HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT
011 = EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN
100 = INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN
101 = INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT, I/O function on RA5/T1CKI/OSC1/CLKIN
110 = EXTRCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
111 = EXTRC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT, RC on RA5/T1CKI/OSC1/CLKIN
Legend:
R = Readable bit
- n = Value at POR
Note 1: Enabling Brown-out Detect does not automatically enable the Power-up Timer (PWRT).
R/P-1
CONFIG – CONFIGURATION WORD (ADDRESS: 2007h)
R/P-1
IESO
BODEN1 BODEN0
R/P-1
R/P-1
(1)
W = Writable bit
‘1’ = Bit is set
Preliminary
R/P-1
CPD
R/P-1
CP
Note:
MCLRE PWRTE
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/P-1
memory space. It belongs to the special
configuration
3FFFh), which can be accessed only during
programming. See “PIC12F6XX/16F6XX
Memory
(DS41204) for more information.
Address 2007h is beyond the user program
R/P-1
(1)
WDTE
R/P-1
Programming
© 2005 Microchip Technology Inc.
memory
x = Bit is unknown
FOSC2
R/P-1
space
F0SC1 F0SC0
R/P-1
Specification”
(2000h-
R/P-1
bit 0