MAX17000AETG+C00 Maxim Integrated Products, MAX17000AETG+C00 Datasheet - Page 18

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MAX17000AETG+C00

Manufacturer Part Number
MAX17000AETG+C00
Description
Other Power Management DDR2 & DDR3 Memory Power-Mgt
Manufacturer
Maxim Integrated Products
Datasheet

Specifications of MAX17000AETG+C00

Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Complete DDR2 and DDR3 Memory
Power-Management Solution
The MAX17000 requires an external 5V bias supply in
addition to the battery. Typically, this 5V bias supply is
the notebook’s 95% efficient 5V system supply.
Keeping the bias supply external to the IC improves
efficiency and eliminates the cost associated with the
5V linear regulator that would otherwise be needed to
supply the PWM circuit and gate drivers. If stand-alone
capability is needed, the 5V supply can be generated
with an external linear regulator such as the MAX1615.
The 5V bias supply powers both the PWM controller
and internal gate-drive power, so the maximum current
drawn is:
where I
is the switching frequency, and Q
total gate-charge specification limits at V
internal MOSFETs.
The Quick-PWM control architecture is a pseudo-fixed-
frequency, constant on-time, current-mode regulator
with voltage feed-forward. This architecture utilizes the
output filter capacitor’s ESR to act as a current-sense
resistor, so the output ripple voltage can provide the
PWM ramp signal. In addition to the general Quick-
PWM, the MAX17000 also senses the inductor current
through DCR method or with a sensing resistor.
Therefore, it is less dependent on the output capacitor
ESR for stability. The control algorithm is simple: the
high-side switch on-time is determined solely by a one-
shot whose pulse width is inversely proportional to input
voltage and directly proportional to output voltage.
Another one-shot sets a minimum off-time (250ns typ).
The on-time one-shot is triggered if the error compara-
tor is low, the low-side switch current is below the valley
current-limit threshold, and the minimum off-time one-
shot has timed out.
The heart of the PWM core is the one-shot that sets the
high-side switch on-time. This fast, low-jitter, adjustable
one-shot includes circuitry that varies the on-time in
response to battery and output voltages. The high-side
switch on-time is inversely proportional to the battery
voltage as measured by the V
to the output voltage.
18
I
BIAS
______________________________________________________________________________________
Q
Free-Running Constant-On-Time PWM
= I
is the current for the PWM control circuit, f
Controller with Input Feed-Forward
Q
+ f
SW
Q
G(MOSFETs)
+5V Bias Supply (V
IN
= 2mA to 20mA (typ)
On-Time One-Shot
input, and proportional
G(MOSFETs)
GS
= 5V for the
DD
, V
is the
CC
SW
)
An external resistor between the input power source
and TON pin sets the switching frequency per phase
according to the following equation:
where C
tion to accommodate for the expected drop across the
low-side MOSFET switch. This algorithm results in a
nearly constant switching frequency despite the lack of
a fixed-frequency clock generator.
For loads above the critical conduction point, where the
dead-time effect is no longer a factor, the actual switch-
ing frequency is:
where V
the inductor discharge path, including synchronous
rectifier, inductor, and PCB resistances; V
sum of the parasitic voltage drops in the charging path,
including the high-side switch, inductor, and PCB resis-
tances; and t
MAX17000.
In skip mode (SKIP = AGND), an inherent automatic
switchover to PFM takes place at light loads. This
switchover is affected by a comparator that truncates
the low-side switch on-time at the inductor current’s
zero crossing.
DC output-accuracy specifications refer to the thresh-
old of the error comparator. When the inductor is in
continuous conduction, the MAX17000 regulates the
valley of the output ripple, so the actual DC output volt-
age is higher than the trip level by 50% of the output
ripple voltage. In discontinuous conduction (SKIP =
AGND and I
a DC regulation level higher than the error-comparator
threshold by approximately 1.5% due to slope compen-
sation. However, the internal integrator corrects for
most of it, resulting in very little load regulation.
STDBY = AGND overrides the SKIP pin setting, forcing
the MAX17000 into standby.
t
ON
DIS
TON
=
C
is the sum of the parasitic voltage drops in
OUT
TON
f
SW
f
= 16.26pF, and 0.075V is an approxima-
SW
Automatic Pulse-Skipping Mode
ON
=
< I
×
=
(
t
is the on-time calculated by the
C
ON
R
LOAD(SKIP)
TON
TON
×
(
V
V
+
×
OUT
IN
6 5
(
R
.
TON
V
k
1
IN
V
+
), the output voltage has
CHG
V
) (
DIS
+
×
6 5
+
V
.
( SKIP = AGND)
CSL
V
k
DIS
)
+
)
0 075
CHG
.
V
is the
)

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