MAX5039EUA Maxim Integrated Products, MAX5039EUA Datasheet - Page 11

• Manufacturer Part Number: MAX5039EUA
• Description: Other Power Management V-Track Ctlr for PowerPC DSPs & ASICs
• Manufacturer: Maxim Integrated Products

Figure 9. Typical Application Circuit for the MAX5039
The MAX5039/MAX5040 provide intelligent control to
power systems where two power supplies need track-
ing. Follow the steps below for designing with the
MAX5039/MAX5040:
1) Select an appropriate external N-channel MOSFET
2) Set the CORE regulation voltage (see the Program-
3) Set the UVLO voltage trip threshold (see the
4) Compensate the CORE linear regulator loop (see
5) Set the POK voltage trip threshold (MAX5040 only,
Figures 9 and 10 show an application example.
SDO is the shutdown signal output. Connect SDO to the
CORE and I/O power-supply shutdown pins. SDO
allows the MAX5039/MAX5040 to control the turning on
and off of the external switching regulators or linear reg-
(see the N-Channel MOSFET Selection section).
ming the CORE Voltage section).
Programming UVLO Voltage section).
the Linear Regulator Compensation section).
see the Programming I/O_SENSE Voltage section).
Designing with MAX5039/MAX5040
1µF
C
IN
______________________________________________________________________________________
V
IN
(5V)
R7
25.5kΩ
1%
R8
10kΩ
1%
IN
IN
Functional Description
UVLO
V
SUPPLY
SUPPLY
CC
POWER
POWER
CORE
I/O
SHDN
SHDN
SDO
MAX5039
OUT
OUT
Voltage-Tracking Controllers for
GND
CORE
CORE_FB
I/O
NDRV
PowerPC, DSPs, and ASICs
S S D D O O
100nF
C1
ulators that supply the CORE and I/O voltages. Using
this single control signal, the MAX5039/MAX5040 turn
the CORE and I/O power supplies on and off together,
minimizing the voltage differential between them.
SDO is low when:
• The voltage on the UVLO pin is below V
• V
• A fault condition is detected.
The MAX5039/MAX5040 prevent premature turn-on of
the CORE and I/O power supplies during power-up by
actively holding SDO low as soon as V
0.9V, provided the condition for SDO to stay low is valid.
NDRV controls the gate of the external N-channel MOSFET
(which is connected between the I/O and CORE voltages),
as needed, as long as V
NDRV is driven high to V
NDRV regulates the external MOSFET as a linear regu-
lator when V
NDRV is driven low when V
> V
(1.230V).
C_REF
CC
1.5nF
C2
Q1
Si9428
SO-8
C
100µF
is below the IC turn-on voltage threshold (2.43V).
CORE
.
10kΩ
R3
I/O
10kΩ
0.1%
R1
V
> V
CORE
V
I/O
= 1.8V AT 2.0A
CORE
= 3.3V AT 2.0A
R2A
9.09kΩ
0.1%
R2B
158Ω
1%
CC
R9
1kΩ
5%
C3
22nF
C
100µF
CC
I/O
and V
is within its operating range.
I/O
when V
50Ω
R4
CORE_FB
> V
CORE
I/O
I/O
CORE
< V
DSP/ASIC
PowerPC/
CC
< V
and V
CORE
C_REF
rises above
CORE_FB
.
NDRV
.
UVCC
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