CAT1640WI-30-G ON Semiconductor, CAT1640WI-30-G Datasheet - Page 6

• Manufacturer Part Number: CAT1640WI-30-G
• Description: Supervisory Circuits CPU w/64K
• Manufacturer: ON Semiconductor

Specifications of CAT1640WI-30-G

• Number Of Voltages Monitored: 1
• Monitored Voltage: 3 V, 3.3 V, 5 V
• Output Type: Active Low, Open Drain
• Manual Reset: Resettable
• Watchdog: No Watchdog
• Battery Backup Switching: No Backup
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 3 V
• Supply Current (typ): 3000 uA
• Maximum Power Dissipation: 1000 mW
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Package / Case: SOIC-8 Wide
• Minimum Operating Temperature: - 40 C
• Power Fail Detection: No
• Undervoltage Threshold: 3 V
• Overvoltage Threshold: 3.15 V
• Power-up Reset Delay (typ): 270 ms
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

DEVICE OPERATION
Reset Controller Description
The CAT1640/41 precision RESET controllers ensure
correct system operation during brownout and power
up/down conditions. They are configured with open-
drain RESET/RESET outputs.
During power-up, the RESET/RESET output remains
active until V
continue driving the outputs for approximately 200ms
(t
interval, the device will cease to drive the reset output.
At this point the reset output will be pulled up or down by
their respective pull up/down resistors.
During power-down, the RESET/RESET output will be
active when V
output will be valid so long as V
The device is designed to ignore the fast negative going
V
Reset output timing is shown in Figure 1.
Manual Reset Operation
The RESET pin can operate as reset output and manual
reset input. The input is edge triggered; that is, the
RESET input will initiate a reset timeout after detecting
a high to low transition.
CAT1640, CAT1641
Doc. No. MD-3012, Rev. D
Figure 1. RESET/RESET Output Timing
PURST
CC
transient pulses (glitches).
RESET
RESET
) after reaching V
V
CC
V
RVALID
CC
CC
V
TH
reaches the V
falls below V
TH
. After the t
TH
CC
TH
. The RESET/RESET
t
PURST
is >1.0V (V
threshold and will
PURST
RVALID
timeout
).
t
GLITCH
6
When RESET I/O is driven to the active state, the 200
msec timer will begin to time the reset interval. If external
reset is shorter than 200 ms, Reset outputs will remain
active at least 200 ms.
Glitches shorter than 100 ns on RESET input will not
generate a reset pulse.
Hardware Data Protection
The CAT1640/41 family has been designed to solve
many of the data corruption issues that have long been
associated with serial EEPROMs. Data corruption occurs
when incorrect data is stored in a memory location which
is assumed to hold correct data.
Whenever the device is in a Reset condition, the embedded
EEPROM is disabled for all operations, including write
operations. If the Reset output is active, in progress
communications to the EEPROM are aborted and no new
communications are allowed. In this condition an internal
write cycle to the memory can not be started, but an in
progress internal non-volatile memory write cycle can not
be aborted. An internal write cycle initiated before the
Reset condition can be successfully finished if there is
enough time (5ms) before VCC reaches the minimum
value of 2V.
t
RPD
t
PURST
Characteristics subject to change without notice.
© 2009 SCILLC. All rights reserved.
t
RPD