PIC16C505-04I/P Microchip Technology Inc., PIC16C505-04I/P Datasheet - Page 32

• Manufacturer Part Number: PIC16C505-04I/P
• Description: 14 PIN, 1.5 KB OTP, 72 RAM, 12 I/O
• Manufacturer: Microchip Technology Inc.

Specifications of PIC16C505-04I/P

• Cpu Speed: 5 MIPS
• Eeprom Memory: 0 Bytes
• Input Output: 11
• Memory Type: OTP
• Number Of Bits: 8
• Package Type: 14-pin PDIP
• Programmable Memory: 1.5K Bytes
• Ram Size: 72 Bytes
• Speed: 4 MHz
• Timers: 1- 8-bit
• Voltage, Range: 2-5.5 V
• Lead Free Status / Rohs Status: RoHS Compliant part Electrostatic Device

PIC16C505
7.3.1
This configuration bit when unprogrammed (left in the
‘1’ state) enables the external MCLR function. When
programmed, the MCLR function is tied to the internal
V
Figure 7-6.
FIGURE 7-6:
7.4
The PIC16C505 family incorporates on-chip Power-On
Reset (POR) circuitry, which provides an internal chip
reset for most power-up situations.
The on chip POR circuit holds the chip in reset until V
has reached a high enough level for proper operation.
To take advantage of the internal POR, program the
RB3/MCLR/V
to V
pull-up resistor is implemented using a transistor. Refer
to Table 10-1 for the pull-up resistor ranges. This will
eliminate external RC components usually needed to
create a Power-on Reset. A maximum rise time for V
is specified. See Electrical Specifications for details.
When the device starts normal operation (exits the
reset condition), device operating parameters (voltage,
frequency, temperature, ...) must be met to ensure
operation. If these conditions are not met, the device
must be held in reset until the operating parameters are
met.
A simplified block diagram of the on-chip Power-On
Reset circuit is shown in Figure 7-7.
DS40192C-page 32
DD
RBWU
, and the pin is assigned to be a I/O. See
DD
or program the pin as RB3. An internal weak
MCLR ENABLE
Power-On Reset (POR)
MCLRE
RB3/MCLR/V
PP
pin as MCLR and tie through a resistor
WEAK
PULL-UP
MCLR SELECT
PP
INTERNAL MCLR
DD
DD
The Power-On Reset circuit and the Device Reset
Timer (Section 7.5) circuit are closely related. On
power-up, the reset latch is set and the DRT is reset.
The DRT timer begins counting once it detects MCLR
to be high. After the time-out period, which is typically
18 ms, it will reset the reset latch and thus end the on-
chip reset signal.
A power-up example where MCLR is held low is
shown in Figure 7-8. V
stabilize before bringing MCLR high. The chip will
actually come out of reset T
goes high.
In Figure 7-9, the on-chip Power-On Reset feature is
being used (MCLR and V
pin is programmed to be RB3.). The V
before the start-up timer times out and there is no
problem
Figure 7-10 depicts a problem situation where V
rises too slowly. The time between when the DRT
senses that MCLR is high and when MCLR and V
actually reach their full value, is too long. In this
situation, when the start-up timer times out, V
not reached the V
function correctly. For such situations, we recommend
that external RC circuits be used to achieve longer
POR delay times (Figure 7-9).
For additional information refer to Application Notes
“ Power-Up Considerations” - AN522 and “ Power-up
Trouble Shooting ” - AN607.
Note:
in
When the device starts normal operation
(exits the reset condition), device operating
parameters (voltage, frequency, tempera-
ture, etc.) must be met to ensure operation.
If these conditions are not met, the device
must be held in reset until the operating
conditions are met.
getting
DD
(min) value and the chip may not
a
DD
1999 Microchip Technology Inc.
DD
proper
is allowed to rise and
are tied together or the
DRT
msec after MCLR
reset.
DD
However,
is stable
DD
has
DD
DD