A3PN030-ZQNG48I Actel, A3PN030-ZQNG48I Datasheet - Page 22

• Manufacturer Part Number: A3PN030-ZQNG48I
• Manufacturer: Actel

ProASIC3 nano DC and Switching Characteristics
2 -8
Power Calculation Methodology
This section describes a simplified method to estimate power consumption of an application. For
more accurate and detailed power estimations, use the SmartPower tool in Actel Libero IDE
software.
The power calculation methodology described below uses the following variables:
Methodology
Total Power Consumption—P
Total Static Power Consumption—P
Total Dynamic Power Consumption—P
Global Clock Contribution—P
Sequential Cells Contribution—P
•
•
•
•
•
•
•
•
P
P
P
P
N
N
P
P
N
Table 2-12 on page
N
on page
F
N
P
P
N
sequential cell is used, it should be accounted for as 1.
α
F
TOTAL
STAT
DYN
CLOCK
CLK
AC1
S-CELL
CLK
STAT
DYN
INPUTS
OUTPUTS
SPINE
ROW
S-CELL
S-CELL
1
is the toggle rate of VersaTile outputs—guidelines are provided in
The number of PLLs as well as the number and the frequency of each output clock
generated
The number of combinatorial and sequential cells used in the design
The internal clock frequencies
The number and the standard of I/O pins used in the design
The number of RAM blocks used in the design
Toggle rates of I/O pins as well as VersaTiles—guidelines are provided in
page
Enable rates of output buffers—guidelines are provided for typical applications in
Table 2-13 on page
Read rate and write rate to the memory—guidelines are provided for typical applications in
Table 2-13 on page
in the design.
, P
is the global clock signal frequency.
is the global clock signal frequency.
= P
= P
is the total dynamic power consumption.
is the total static power consumption.
is the number of VersaTile rows used in the design—guidelines are provided in
= P
= N
AC2
= (P
is the number of global spines used in the user design—guidelines are provided in
is the number of VersaTiles used as sequential modules in the design.
is the number of VersaTiles used as sequential modules in the design. When a multi-tile
is the number of I/O input buffers used in the design.
CLOCK
DC1
2-10.
2-10.
STAT
is the number of I/O output buffers used in the design.
, P
S-CELL
AC1
+ N
AC3
+ P
+ P
+ N
INPUTS
, and P
* (P
DYN
S-CELL
SPINE
AC5
2-10.
* P
*P
AC4
+ P
+
2-10.
2-10. The calculation should be repeated for each clock domain defined
DC2
AC2
α
C-CELL
are device-dependent.
1
+ N
+ N
/ 2 * P
CLOCK
TOTAL
OUTPUTS
ROW
+ P
A dv a n c e v 0. 2
S-CELL
AC6
NET
*P
STAT
) * F
AC3
* P
+ P
DYN
DC3
INPUTS
+ N
CLK
S-CELL
+ P
* P
OUTPUTS
AC4
) * F
+ P
CLK
MEMORY
+ P
Table 2-12 on page
PLL
Table 2-12 on
Table 2-12
2-10.