PIC32MX420F032H-40V/MR Microchip Technology, PIC32MX420F032H-40V/MR Datasheet - Page 41

• Manufacturer Part Number: PIC32MX420F032H-40V/MR
• Description: 32 KB Flash, 8 KB RAM, USB-OTG, 40 MHz, 10-Bit ADC, DMA 64 QFN 9x9x0.9mm TUBE
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX420F032H-40V/MR

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 32 KB
• Data Ram Size: 8 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: QFN-64
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Eeprom Size: -
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

3.3
The MIPS32
of power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
supports slowing or halting the clocks, which reduces
system power consumption during idle periods.
3.3.1
The mechanism for invoking power-down mode is
through execution of the WAIT instruction. For more
information on power management, see
“Power-Saving
3.3.2
The majority of the power consumed by the
PIC32MX3XX/4XX family core is in the clock tree and
clocking registers. The PIC32MX family uses extensive
use of local gated-clocks to reduce this dynamic power
consumption.
© 2011 Microchip Technology Inc.
Power Management
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
LOCAL CLOCK GATING
®
M4K
Features”.
®
Processor Core offers a number
Section 25.0
3.4
The MIPS32
Enhanced JTAG (EJTAG) interface for use in the
software debug of application and kernel code. In
addition to standard user mode and kernel modes of
operation, the core provides a Debug mode that is
entered after a debug exception (derived from a
hardware breakpoint, single-step exception, etc.) is
taken and continues until a debug exception return
(DERET) instruction is executed. During this time, the
processor executes the debug exception handler
routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for
transferring test data in and out of the core. In addition
to the standard JTAG instructions, special instructions
defined in the EJTAG specification define what
registers are selected and how they are used.
PIC32MX3XX/4XX
EJTAG Debug Support
®
M4K
®
Processor Core provides for an
DS61143H-page 41