PIC32MX460F512LT-80V/BG Microchip Technology, PIC32MX460F512LT-80V/BG Datasheet - Page 40

• Manufacturer Part Number: PIC32MX460F512LT-80V/BG
• Description: 512 KB Flash, 32 KB RAM, USB-OTG, 80 MHz, 10-Bit ADC, DMA 121 XBGA 10x10x1.20mm
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX460F512LT-80V/BG

• Processor Series: PIC32MX4xx
• Core: MIPS
• Data Bus Width: 32 bit
• Program Memory Type: Flash
• Program Memory Size: 512 KB
• Data Ram Size: 32 KB
• Interface Type: USB, I2C, UART, RS-232, RS-485, SPI
• Maximum Clock Frequency: 80 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 5
• Operating Supply Voltage: 2.3 V to 3.6 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Package / Case: XBGA-121
• Operating Temperature Range: - 40 C to + 105 C
• Supply Current (max): 10 mA
• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: -
• Eeprom Size: -
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Lead Free Status / Rohs Status: Details

PIC32MX3XX/4XX
TABLE 3-2:
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors.
shows the exception types in order of priority.
TABLE 3-3:
DS61143H-page 40
Note 1:
Register
Number
DDBL/DDBS
17-22
25-29
Exception
23
24
30
31
Interrupt
DDBL
Reset
AdES
AdEL
AdEL
DINT
CEU
DSS
CpU
DBE
NMI
DBp
DIB
IBE
Sys
2:
Ov
Bp
RI
Tr
Registers used in exception processing.
Registers used during debug.
Register
Name
Reserved
Debug
DEPC
Reserved
ErrorEPC
DESAVE
COPROCESSOR 0 REGISTERS (CONTINUED)
PIC32MX3XX/4XX FAMILY CORE EXCEPTION TYPES
(2)
Assertion MCLR or a Power-on Reset (POR)
EJTAG Debug Single Step
EJTAG Debug Interrupt. Caused by the assertion of the external EJ_DINT input, or by setting the
EjtagBrk bit in the ECR register
Assertion of NMI signal
Assertion of unmasked hardware or software interrupt signal
EJTAG debug hardware instruction break matched
Fetch address alignment error
Fetch reference to protected address
Instruction fetch bus error
EJTAG Breakpoint (execution of SDBBP instruction)
Execution of SYSCALL instruction
Execution of BREAK instruction
Execution of a Reserved Instruction
Execution of a coprocessor instruction for a coprocessor that is not enabled
Execution of a CorExtend instruction when CorExtend is not enabled
Execution of an arithmetic instruction that overflowed
Execution of a trap (when trap condition is true)
EJTAG Data Address Break (address only) or EJTAG Data Value Break on Store (address + value)
Load address alignment error
Load reference to protected address
Store address alignment error
Store to protected address
Load or store bus error
EJTAG data hardware breakpoint matched in load data compare
(2)
(2)
(1)
Function
Reserved
Debug control and exception status
Program counter at last debug exception
Reserved
Program counter at last error
Debug handler scratchpad register
Table 3-3
Description
© 2011 Microchip Technology Inc.