PIC32MX575F512L-80V/PF Microchip Technology, PIC32MX575F512L-80V/PF Datasheet - Page 54

• Manufacturer Part Number: PIC32MX575F512L-80V/PF
• Description: 512 KB Flash, 64 KB RAM, USB-OTG, CAN, 80 MHz, 10-Bit ADC, DMA 100 TQFP 14x14x1m
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX575F512L-80V/PF

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: CAN, I²C, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 85
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 64K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

supports slowing or Halting the clocks, which reduces
PIC32MX5XX/6XX/7XX
3.3
The MIPS M4K Processor core offers a number of
power management features, including low-power
design, active power management and power-down
modes of operation. The core is a static design that
system power consumption during Idle periods.
3.3.1
The mechanism for invoking Power-Down mode is
through execution of the WAIT instruction. For more
information on power management, see
“Power-Saving
3.3.2
The majority of the power consumed by the
PIC32MX5XX/6XX/7XX family core is in the clock tree
and clocking registers. The PIC32 family uses exten-
sive use of local gated clocks to reduce this dynamic
power consumption.
DS61156G-page 54
Power Management
INSTRUCTION-CONTROLLED
POWER MANAGEMENT
LOCAL CLOCK GATING
Features”.
Section 27.0
3.4
The MIPS M4K Processor core provides for an
Enhanced JTAG (EJTAG) interface for use in the soft-
ware debug of application and kernel code. In addition
to standard User mode and Kernel modes of operation,
the MIPS M4K core provides a Debug mode that is
entered after a debug exception (derived from a hard-
ware breakpoint, single-step exception, etc.) is taken
and continues until a Debug Exception Return (DERET)
instruction is executed. During this time, the processor
executes the debug exception handler routine.
The EJTAG interface operates through the Test Access
Port (TAP), a serial communication port used for trans-
ferring test data in and out of the MIPS M4K processor
core. In addition to the standard JTAG instructions,
special instructions defined in the EJTAG specification
define which registers are selected and how they are
used.
EJTAG Debug Support
© 2009-2011 Microchip Technology Inc.