DS2186 Maxim Integrated Products, DS2186 Datasheet
DS2186
Specifications of DS2186
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DS2186 Summary of contents
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... Companion to the DS2187 Receive Line Interface and DS2188 T1/CEPT Jitter Attenuator Single 5V supply; low–power CMOS technology DESCRIPTION The DS2186 T1/CEPT Transmit Line Interface Chip in- terfaces user equipment to North American (T1–1.544 MHz) and European (CEPT–2.048 MHz) primary rate communications networks. The device is compatible with all types of twisted pair and coax cable found in such networks ...
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... DS2186 DS2186 BLOCK DIAGRAM Figure 1 VSS LNEG LPOS LCLK INPUT ZERO CODE DATA SUPPRESSION TNEG MUX CIRCUITRY TPOS TCLK LB ZCSEN TAIS TCLKSEL SYSTEM LEVEL INTERCONNECT Figure 2 DS2187 AVDD LCAP ZCSEN RCLKSEL RTIP RRING RECEIVE PAIR LOCK AVSS 1:2 DS2186 VDD ZCSEN ...
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... T1 long loop (CSU; 0 dB, –7.5 dB and –15 dB) and CEPT (CCITT G.703) pulse template requirements. On–chip laser trimmed delay lines clocked by either TCLK or LCLK control a precision digital–to–analog converter to build the desired waveforms, which are buffered differentially by the line drivers. DS2186 022798 3/11 ...
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... DS2186 The shape of the “pre–emphasized” T1 waveform is controlled by inputs LEN0, LEN1, and LEN2 (TCLKSEL=0). These control inputs allow the user to select the appropriate output pulse shape to meet DSX–1 or CSU templates over a wide variety of cable types and lengths. Those cable types include ABAM, PIC, and PULP ...
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... NANOSECONDS 022798 5/11 DS2186 ...
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... DS2186 OUTPUT PULSE TEMPLATE AT 2.048 MHz Figure 4 1.2 1.0 NORMALIZED AMPLITUDE 0.5 0.0 –0.2 NOTES: 1. Unlike the DSX–1 template, which is specified at the cross–connect point, the CEPT (2.048 MHz) template is spe- cified at the transmit line output. 2. The template shown above is normalized. The actual pulse height is cable dependent and is specified in Table 3 ...
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... AMI or HDB3 120 ohm Resistive (wire pair) 75 ohm Resistive (coax) 3.0V (wire pair) 2.37V (coax) –Scaled to fit templates shown– 244 ns 1) Negative peak = positive peak 5% 2) Positive width at nominal half ampli- tude = negative width at nominal half amplitude 5%. DS2186 022798 7/11 ...
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... DS2186 ABSOLUTE MAXIMUM RATINGS* Voltage on any Pin Relative to Ground Operating Temperature Storage Temperature Soldering Temperature * This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. Exposure to absolute maxi- mum rating conditions for extended periods of time may affect reliability ...
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... Falling LPOS, LNEG Hold from LCLK t HTD Falling NOTES applications. 2. CEPT applications. AC TIMING DIAGRAM Figure 5 TCLK, LCLK t t STD HTD TPOS, TNEG LPOS, LNEG ( MIN TYP MAX UNITS 648 ns 488 ns 70 324 ns 70 244 CLK RWH RWL DS2186 5%) NOTES 022798 9/11 ...
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... DS2186 DS2186 TRANSMIT LINE INTERFACE 20–PIN DIP 022798 10/11 PKG 20–PIN DIM MIN A IN. 1.020 B MM 25.91 B IN. 0.240 MM 6.10 C IN. 0.120 MM 3.05 D IN. 0.300 MM 7.62 E IN. 0.015 MM 0.38 F IN. 0.120 MM 3. IN. 0.090 MM 2.23 H IN. 0.320 IN. 0.008 MM 0.20 K IN. ...
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... DS2186S TRANSMIT LINE INTERFACE 20–PIN SOIC phi L J PKG 20–PIN DIM MIN A IN. 0.500 MM 12.70 B IN. 0.290 7.37 C IN. 0.089 MM 2.26 E IN. 0.004 MM 0.102 F IN. 0.094 MM 2.38 0.050 BSC G IN. 1.27 BSC MM H IN. 0.398 MM 10.11 J IN. 0.009 MM 0.229 C K IN. 0.013 MM 0. ...