DS2181A Maxim Integrated Products, DS2181A Datasheet
DS2181A
Specifications of DS2181A
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DS2181A Summary of contents
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... SDI 15 SDO SCLK 18 SPS 19 VSS 20 40-Pin DIP (600-mil) TSER 7 TMO 8 TXD 9 TSTS 10 TSD 11 44-PIN PLCC TIND 12 TAF 13 TPOS 14 TNEG 15 INT 16 SDI DS2181A 40 VDD 39 RLOS 38 RFER 37 RBV 36 RCL 35 RNEG 34 RPOS 33 RST 32 TEST 31 RCSYNC 30 RSTS 29 RSD 28 RMSYNC 27 RFSYNC 26 RSER 25 RCHCLK 24 RCLK 23 RAF 22 RDMA ...
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... DESCRIPTION The DS2181A is designed for use in CEPT networks and supports all logical requirements of CCITT Red Book Recommendations G.704, G.706 and G.732. The transmit side generates framing patterns and CRC4 codes, formats outgoing channel and signaling data, and produces network alarm codes when enabled ...
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... Receive CRC4 Time Out. This pin will transition high when the RCTO counter reaches its maximum count of 32. The pin will return low when either the DS2181AQ reaches CRC4 multiframe synchronization CRC4 is disabled via CRC. the device is issued a hardware reset via the Receive CRC4 Search Active ...
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... NOTES: 1. These output status pins are only available on the DS2181AQ the TEST pin is tied low and CCR.1=0, then these pins will be tri–stated. RECEIVE PIN DESCRIPTION (40-PIN DIP ONLY) Table 2B PIN SYMBOL TYPE 21 RRA O 22 RMDA O 23 RAF O 24 RCLK I 25 ...
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... Signal Ground. 0.0 volts. Test Mode. Tie select the old DS2181 sync algorithm and to SS tri–state the synchronizer status pins on the DS2181AQ. Tie select the new DS2181A sync algorithm and activate the synchronizer status pins on the DS2181AQ. Positive Supply. 5.0 volts. ...
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... RSR is a read only register; all other registers are read/write. 3. Reserved bit locations must be programmed to 0. SERIAL PORT INTERFACE Pins 14 through 18 of the DS2181A serve as a microprocessor/ microcontroller-compatible serial port. Fourteen on-chip registers allow the user to update operational characteristics and monitor device status via a host controller, minimizing hardware interfaces. ...
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... Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or write is enabled. Reserved, must be 0 for proper operation. Reserved, must be 0 for proper operation. MSB of register address. LSB of register address. Read/Write Select write addressed register read addressed register DS2181A (LSB) ADD1 AD0 R/ W ...
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... Source extra bits from TXR.0 through TXR.1 and TXR.3. Transmit Signaling All 1’ Normal operation Force contents of timeslot 16 in all frames to all 1’s. Output Data Mode 0 = TPOS and TNEG outputs are 100% duty cycle TPOS and TNEG outputs are 50% duty cycle DS2181A (LSB) XBS TSA1 ODM ...
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... Disable CRC4 multiframe synchronizer Enable CRC4 synchronizer; search for CRC4 multiframe alignment once frame alignment complete. Sync Algorithm Select 0 = Use old DS2181 sync algorithm 1 = Use new DS2181A sync algorithm Local Loopback 0 = Normal operation Internally loop TPOS, TNEG, and TCLK to RPOS, RNEG, and RCLK. ...
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... Outputs TAF and RAF indicate frames which contain the alignment signal. Timeslot 0 of frames not containing the frame alignment signal is used for alarm and national data. See the separate DS2181A CEPT Transceiver Application Note for more details. CAS SIGNALLING CEPT networks support Channel Associated Signaling (CAS) or Common Channel Signaling (CCS) ...
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... RMSYNC and/or RCSYNC are then updated. Output RLOS is held high during the entire resync process, then transitions low after the last output timing update indicating resync is complete. For more details about the receive synchronizer, see the separate DS2181A CEPT Transceiver Application Note. FIXED FRAME SYNC CRITERIA Valid frame sync is assumed when the correct frame alignment signal is present in frame N and frame and not present in frame (bit 2 of timeslot 0 of Frame also checked for 1) ...
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... When enabled via RCR.1, the device will automatically initiate frame search whenever two consecutive CAS multiframe alignment words are received in error. FIXED CRC4 RESYNC CRITERIA If CCR.1 the TEST pin is tied high, then the DS2181A will initiate the resync at the FAS level if 915 or more CRC4 words out of 1000 are received in error. CAS SIGNALLING SOURCE CAS applications sample signaling data at TSER when TCR ...
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... Normal operation; bit 3 of timeslot 0 in non-alignment frame clear Alarm condition; bit 3 of timeslot 0 in non-align frames set. Transmit National Bits. Inserted into the outgoing data stream at TPOS and TNEG when TCR FRAME 15 ABCD for ABCD for Timeslot 15 Timeslot 31 (LSB) NB6 NB7 DS2181A NB8 ...
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... TS28 TS27 TS26 NAME AND DESCRIPTION Transmit Idle Registers Each of these bit positions represents a timeslot in the outgoing stream at TPOS and TNEG; when set, the contents of that timeslot are forced to idle code (11010101 DS2181A (LSB) TDMA XB2 XB3 (LSB) 1 TS1 TS0 TIR1 ...
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... Output TAF also indicates frames containing the frame alignment signal. Those frames can be even or odd numbering frames of the outgoing CAS multiframe (CCR.6). TRANSMIT MULTIFRAME TIMING Figure 12 NOTES: 1. Alignment frames are even frames of the CAS and/or CRC4 multiframes (CCR.6 = 0). 2. Alignment frames are odd frames of the CAS multiframe (CCR DS2181A ...
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... RECEIVE SIGNALING Receive signaling data is available at two outputs: RSER and RSD. RSER outputs the signaling data in timeslot 16 at RSER. The signaling data is also extracted from timeslot 16 and presented at RSD during the timeslots shown in Table 7. This channel-associated signaling simplifies CAS system design DS2181A ...
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... The receive side output timing set is identical to that found on the transmit side. The user can tie receive outputs directly to the transmit inputs for drop and insert applications. The received data of RPOS, RNEG appear at RSER after six RCLK delays, without any change except for the HDB3-to-NRZ conversion when HDB3 is enabled DS2181A ...
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... NOTE: 1. The CAS multiframe can start with an align or non-align frame. The CRC4 multiframe always starts with an align frame. RSD TIMING Figure DS2181A ...
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... NOTES: 1. Low-high transitions on RMSYNC and RFSYNC occur one RCLK period early with respect to actual frame and multiframe boundaries. 2. RAF transitions on true frame boundaries. 3. Delay from RPOS, RNEG to RSER is six RCLK periods. 4. RMSYNC and RCSYNC transition low on the falling edge of RFSYNC DS2181A ...
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... CAS Multiframe Resync Criteria Met. Set when the CAS multiframe error criteria are met; also, the frame resync is initiated if RCR.1=0. Receive Loss of Sync. Set when resync is in progress. Error Counter Saturation. Set when any of the on-chip counters at FECR, CECR or BVCR saturates DS2181A (LSB) RLOS ECS ...
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... CAS Multiframe Resync Criteria Met 1 = Interrupt enabled 0 = Interrupt masked Receive Loss of Sync 1 = Interrupt enabled 0 = Interrupt masked Error Count Saturation 1 = Interrupt enabled 0 = Interrupt masked BVD4 BVD3 NAME AND DESCRIPTION MSB of bipolar violation count. LSB of bipolar violation count DS2181A (LSB) RLOS ECS (LSB) BVD2 BVD1 BVD0 ...
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... ALARM OUTPUTS Alarm conditions are also reported real time at alarm outputs. These outputs can be used with off-chip logic to complement the on-chip error reporting capability of the DS2181A. In the hardware mode, they are the only alarm reporting means available. RLOS The RLOS output indicates the status of the receive synchronizer ...
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... CRC4 code words are in error. The FECR and CECR log error events reported at this output. FECR logs only the frame alignment word errors. CECR logs CRC4 code word errors. To complement the on-chip error logging capabilities of the DS2181A, the system designer can use off- chip logic gated by receive side outputs RCHCLK, RAF, RSTS and RCSYNC to demux error states present at RFER ...
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... FRAME ALIGNMENT WORD ERRORED Figure 26 CRC4 SUB-MULTIFRAME 1 ERRORED Figure 27 NOTES FOR FIGURES 23 THROUGH 27: 1. CAS multiframe alignment word received in error; RFER will transition high at first error occurrence and remain high as shown. 2. Previous CRC4 sub-multiframe 2 errored. 3. Frame alignment word errored. 4. Previous CRC4 sub-multiframe 1 errored DS2181A ...
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... TXR.2 Alarm 0 = Normal operation 1 = Enable alarm Data Format CCR.5/CCR Input and output data AMI coded 1 = Input and output data HDB3 coded Transmit and Receive CRC4 Multiframe CCR.3/CCR Disabled 1 = Enabled Transmit and Receive CAS Multiframe TCR.5/RCR Enabled 1 = Disabled NAME AND DESCRIPTION DS2181A ...
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... Applies to SDO when tri-stated. -1.0V to +7.0V 0° to 70°C -55°C to +125°C 260°C for 10 seconds SYMBOL MIN TYP SYMBOL MIN TYP - DS2181A ( MAX UNITS NOTES V +. +0 5.0V ± 10%) DD MAX UNITS NOTES 10 mA 1,2 +1.0 µ +1.0 µA 6 ...
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... SERIAL PORT WRITE AC TIMING DIAGRAM Figure 28 NOTE: 1. Shaded regions indicate “don’t care” states of input data. 1 SERIAL PORT READ AC TIMING Figure 29 NOTE: 1. Serial port write must precede a port read to provide address information DS2181A ...
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... V and 10 ns maximum rise and fall time. 1,2 – TRANSMIT SYMBOL MIN TYP t 488 244 WL STD t 50 HTD t 75 STS t 50 HTS t PTS = .8V and 10 ns maximum rise and fall time 5.0V ± 5%) DD MAX UNITS 100 200 5.0V ± 5%) DD MAX UNITS DS2181A NOTES NOTES ...
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... Output Capacitance 1,2 – RECEIVE SYMBOL MIN t PRS t PRD t TTR WL SRD t 50 HRD t PRA t 1 RST = .8V and 10 ns maximum rise and fall times. IL SYMBOL MIN OUT 5.0V ± 5%) DD TYP MAX UNITS 488 ns 244 µ TYP MAX UNITS DS2181A NOTES =25 C) NOTES ...
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... TRANSMIT AC TIMING DIAGRAM Figure 30 RECEIVE AC TIMING DIAGRAM Figure DS2181A ...
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... DS2181A CEPT TRANSCEIVER (600-MIL DIP) 40-PIN DIM INCHES MIN MAX 2.050 2.075 0.530 0.550 0.140 0.160 0.600 0.625 0.015 0.040 0.120 0.145 0.090 0.110 0.625 0.675 0.008 0.012 0.015 0.022 DS2181A ...
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... DS2181AQ CEPT TRANSCEIVER (PLCC) DIM CH1 INCHES MIN MAX 0.165 0.180 0.090 0.120 0.020 - 0.026 0.033 0.013 0.021 0.009 0.012 0.042 0.048 0.685 0.695 0.650 0.656 0.590 0.630 0.685 0.695 0.650 0.656 0.590 0.630 0.050 BSC DS2181A ...