DS2181AQ Maxim Integrated Products, DS2181AQ Datasheet - Page 7

• Manufacturer Part Number: DS2181AQ
• Description: IC TXRX CEPT PRIMARY RATE 44PLCC
• Manufacturer: Maxim Integrated Products
• Type: Transceiverr

Specifications of DS2181AQ

• Number Of Drivers/receivers: 1/1
• Protocol: CEPT
• Voltage - Supply: 4.5 V ~ 5.5 V
• Mounting Type: Surface Mount
• Package / Case: 44-LCC, 44-PLCC
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

ADDRESS/COMMAND
An address/command byte write must precede any read or write of the port registers. The first bit written
(LSB) of the address/command byte specifies read or write. The following nibble identifies register
address. The next 2 bits are reserved and must be set to 0 for proper operation. The last bit of the
address/command word enables the burst mode when set; the burst mode allows consecutive reading or
writing of all register data. Data is written to and read from the port LSB first.
CHIP SELECT AND CLOCK CONTROL
All data transfers are initiated by driving the
Data is output on the falling edge of SCLK and held to the next falling edge. All data transfers are
terminated and SDO tri-stated when
CLOCKS
To access the serial port registers both TCLK and RCLK are required along with the SCLK. The TCLK
and RCLK are used to internally access the transmit and receive registers, respectively. The CCR is
considered a receive register for this purpose.
DATA I/O
Following the eight SCLK cycles that input the address/ command byte, data at SDI is strobed into the
addressed register on the next eight SCLK cycles (register write) or data is presented at SDO on the next
eight SCLK cycles (register read). SDO is tri-stated during writes and may be tied to SDI in applications
where the host processor has bi-directional I/O capability.
BURST MODE
The burst mode allows all on-chip registers to be consecutively read or written by the host processor. This
feature minimizes device initialization time on system power-up or reset. Burst mode is initiated when
ACB.7 is set and the address nibble is 0000. All registers must be read or written during the burst mode.
If
ACB: ADDRESS COMMAND BYTE Figure 2
(MSB)
SYMBOL
CS
BM
ADD3
ADD2
ADD1
ADD0
R/W
BM
transitions high before the burst is complete, data validity is not guaranteed.
-
-
-
POSITION
ACB.7
ACB.6
ACB.5
ACB.4
ACB.3
ACB.2
ACB.1
ACB.0
-
CS
NAME AND DESCRIPTION
Burst Mode. If set (and ACB.1 through ACB.4=0) burst read or
write is enabled.
Reserved, must be 0 for proper operation.
Reserved, must be 0 for proper operation.
MSB of register address.
LSB of register address.
Read/Write Select.
0 = write addressed register.
1 = read addressed register.
returns to high.
ADD3
CS
input low. Data is sampled on the rising edge of SCLK.
7 of 32
ADD2
ADD1
AD0
(LSB)
DS2181A
R/
W