AD8016ARE

Manufacturer Part NumberAD8016ARE
DescriptionIC AMP XDSL LINE DVR 28-TSSOP
ManufacturerAnalog Devices Inc
TypeDriver
AD8016ARE datasheet
 


Specifications of AD8016ARE

Rohs StatusRoHS non-compliantNumber Of Drivers/receivers2/0
ProtocolxDSLVoltage - Supply3 V ~ 13 V
Mounting TypeSurface MountPackage / Case28-TSSOP Exposed Pad, 28-eTSSOP, 28-HTSSOP
Power Supply RequirementDualPackage TypeTSSOP EP
Slew Rate1000V/usPin Count28
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THEORY OF OPERATION
The AD8016 is a current feedback amplifier with high (500 mA)
output current capability. With a current feedback amplifier, the
current into the inverting input is the feedback signal and the
open-loop behavior is that of a transimpedance, dV
The open-loop transimpedance is analogous to the open-loop
voltage gain of a voltage feedback amplifier. Figure 37 shows a
simplified model of a current feedback amplifier. Since R
proportional to 1/g
, the equivalent voltage gain is just T
m
where g
is the transconductance of the input stage. Basic
m
analysis of the follower with gain circuit yields
V
T S
O
=
×
Z
G
+
V
T S
( )
G
IN
Z
where:
R
=
+
F
G
1
R
G
1
=
25 Ω
R
IN
g
m
Recognizing that G × R
<< R
for low gains, the familiar
IN
F
result of constant bandwidth with gain for current feedback
amplifiers is evident, the 3 dB point being set when |T
Of course, for a real amplifier there are additional poles that
contribute excess phase and there is a value for R
the amplifier is unstable. Tolerance for peaking and desired flatness
determines the optimum R
in each application.
F
R
F
R
G
R
IN
+
I
T
IN
Z
R
N
+
V
IN
Figure 37. Simplified Block Diagram
The AD8016 is the first current feedback amplifier capable of
delivering 400 mA of output current while swinging to within
2 V of either power supply rail. This enables full CO ADSL
performance on only 12 V rails, an immediate 20% power saving.
The AD8016 is also unique in that it has a power management
system included on-chip. It features four user programmable
power levels (all of which provide a low output impedance of the
driver), as well as the provision for complete shutdown (high
impedance state). Also featured is a thermal shutdown with
alarm signal.
POWER SUPPLY AND DECOUPLING
The AD8016 should be powered with a good quality (i.e., low
noise) dual supply of ± 12 V for the best distortion and multitone
power ratio (MTPR) performance. Careful attention must be
paid to decoupling the power supply pins. A 10 µF capacitor
located in near proximity to the AD8016 is required to pro-
vide good decoupling for lower frequency signals. In addition,
0.1 µF decoupling capacitors should be located as close to
each of the four power supply pins as is physically possible.
All ground pins should be connected to a common low imped-
ance ground plane.
REV. B
FEEDBACK RESISTOR SELECTION
In current feedback amplifiers, selection of feedback and gain
resistors has an impact on the MTPR performance, bandwidth,
and gain flatness. Care should be taken in selecting these resis-
/dI
or T
.
tors so that optimum performance is achieved. The table below
O
IN
Z
shows the recommended resistor values for use in a variety of
gain settings. These values are suggested as a good starting
point when designing for any application.
is
IN
× g
,
Z
m
( )
×
+
R
R
IN
F
BIAS PIN AND PWDN FEATURES
The AD8016 is designed to cover both CO (central office) and
CPE (customer premise equipment) ends of an xDSL applica-
tion. It offers full versatility in setting quiescent bias levels for
the particular application from full ON to reduced bias (in three
steps) to full OFF (via BIAS pin). This versatility gives the
modem designer the flexibility to maximize efficiency while
| = R
.
maintaining reasonable levels of multitone power ratio (MTPR)
Z
F
performance. Optimizing driver efficiency while delivering the
below which
required DMT power is accomplished with the AD8016 through
F
the use of on-chip power management features. Two digitally
programmable logic pins, PWDN1 and PWDN0, may be used
to select four different bias levels: 100%, 60%, 40%, and 25%
of full quiescent power (see Table II).
V
OUT
PWDN1
Code
1
1
0
0
X
The bias level can be controlled with TTL logic levels (High = 1)
applied to the PWDN1 and PWDN0 pins alone or in combina-
tion with the BIAS control pin. The DGND or digital ground
pin is the logic ground reference for the PWDN1 and PWDN0
pins. In typical ADSL applications where ± 12 V or ± 6 V
supplies (also single supplies) are used, the DGND pin is
connected to analog ground.
The BIAS control pin by itself is a means to continuously adjust
the AD8016 internal biasing and thus quiescent current I
pulling out a current of 0 µA (or open) to approximately 200 µA,
the quiescent current can be adjusted from 100% (full ON) to a
full OFF condition. The full OFF condition yields a high output
impedance. Because of an on-chip resistor variation of up to
± 20%, the actual amount of current required to fully shut down
the AD8016 can vary. To institute a full chip shutdown, a pull-
down current of 250 µA is recommended. See Figure 38 for the
logic drive circuit for complete amplifier shutdown. Figures 34
and 35 show the relationship between current pulled out of the
–11–
Table I. Resistor Selection Guide
Gain
R
( )
R
F
+1
1000
–1
500
500
+2
650
650
+5
750
187
+10
1000
111
Table II. PWDN Code Selection Guide
PWDN0
Code
Quiescent Bias Level
1
100% (Full ON)
0
60%
1
40%
0
25% (Low Z
OUT
X
Full OFF (High Z
Pulled Out of BIAS Pin)
AD8016
( )
G
but Not OFF)
via 250 µA
OUT
. By
Q