ADV7188BSTZ Analog Devices Inc, ADV7188BSTZ Datasheet - Page 67

• Manufacturer Part Number: ADV7188BSTZ
• Description: IC DECODER VID MULTIFORM 80LQFP
• Manufacturer: Analog Devices Inc
• Type: Video Decoderr

Specifications of ADV7188BSTZ

• Applications: Set-Top Boxes, Video Players, Recorders
• Voltage - Supply, Analog: 3.15 V ~ 3.45 V
• Voltage - Supply, Digital: 1.65 V ~ 2 V
• Mounting Type: Surface Mount
• Package / Case: 80-LQFP
• Resolution (bits): 12bit
• Input Format: Analog
• Output Format: Digital
• Adc Sample Rate: 54MSPS
• No. Of Input Channels: 12
• Supply Voltage Range: 3V To 3.6V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

VITC
VITC has a sequence of 10 syncs in between each data byte. The
VDP strips these syncs from the data stream to output only the data
bytes. The VITC results are available in the VDP_VITC_DATA_0
to VDP_VITC_DATA_8 registers (Register 0x92 to Register 0x9A,
user sub map).
The VITC has a CRC byte at the end; the syncs in between each
data byte are also used in this CRC calculation. Because these syncs
are not output, the CRC is calculated internally. The calculated
CRC is also available for the user in the VDP_VITC_CALC_CRC
register (Register 0x9B, User Sub Map). After the VDP completes
decoding the VITC line, the VDP_VITC_DATA_x and
VDP_VITC_CALC_CRC registers are updated and the
VITC_AVL bit is set.
Table 81. VITC Readback Registers
Signal Name
VITC_DATA_0 [7:0]
VITC_DATA_1 [7:0]
VITC_DATA_2 [7:0]
VITC_DATA_3 [7:0]
VITC_DATA_4 [7:0]
VITC_DATA_5 [7:0]
VITC_DATA_6 [7:0]
VITC_DATA_7 [7:0]
VITC_DATA_8 [7:0]
VITC_CALC_CRC [7:0]
1
The register is a readback register; the default value does not apply.
Register Location
VDP_VITC_DATA_0 [7:0] (VITC Bits [9:2])
VDP_VITC_DATA_1 [7:0] (VITC Bits [19:12])
VDP_VITC_DATA_2 [7:0] (VITC Bits [29:22])
VDP_VITC_DATA_3 [7:0] (VITC Bits [39:32])
VDP_VITC_DATA_4 [7:0] (VITC Bits [49:42])
VDP_VITC_DATA_5 [7:0] (VITC Bits [59:52])
VDP_VITC_DATA_6 [7:0] (VITC Bits [69:62])
VDP_VITC_DATA_7 [7:0] (VITC Bits [79:72])
VDP_VITC_DATA_8 [7:0] (VITC Bits [89:82])
VDP_VITC_CALC_CRC [7:0]
BIT 0, BIT 1
1
Figure 42. VITC Waveform and Decoded Data Correlation
Rev. A | Page 67 of 112
VITC WAVEFORM
TO
VITC_CLEAR, VITC Clear, Address 0x78 [6],
User Sub Map, Write Only, Self-Clearing
1—Reinitializes the VITC readback registers.
VITC_AVL, VITC Available, Address 0x78 [6],
User Sub Map
0—VITC data was not detected.
1—VITC data was detected.
VITC Readback Registers
See Figure 42 for the I
2
C to VITC bit mapping.
BIT 88, BIT 89
Dec
146d
147d
148d
149d
150d
151d
152d
153d
154d
155d
Address (User Sub Map)
Hex
0x92
0x93
0x94
0x95
0x96
0x97
0x98
0x99
0x9A
0x9B
ADV7188