ADV7194KST Analog Devices Inc, ADV7194KST Datasheet
ADV7194KST
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ADV7194KST Summary of contents
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... IN 4:2:2 FORMAT YUV MATRIX Extended- trademark of Analog Devices, Inc. This technology combines 10-bit conversion, 10-bit digital video data processing, and 10-bit external interfacing. SSAF is a trademark of Analog Devices Inc. ITU-R and CCIR are used interchangeably in this document (ITU-R has replaced CCIR recommendations registered trademark of Philips Corporation ...
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ADV7194 CONTENTS FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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SPECIFICATIONS ( SPECIFICATIONS otherwise noted.) Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) 3 Integral Nonlinearity 3 Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL ...
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ADV7194–SPECIFICATIONS (V 1 3.3 V SPECIFICATIONS unless otherwise noted.) Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity DIGITAL INPUTS Input High Voltage, V INH Input Low Voltage, V INL Input Current Input Capacitance, ...
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V DYNAMIC SPECIFICATIONS Parameter Hue Accuracy Color Saturation Accuracy Chroma Nonlinear Gain Chroma Nonlinear Phase Chroma/Luma Intermod Chroma/Luma Gain Ineq Chroma/Luma Delay Ineq Luminance Nonlinearity Chroma AM Noise Chroma PM Noise 3 Differential Gain 3 Differential Phase 3 SNR ...
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ADV7194 5 V TIMING CHARACTERISTICS Parameter 2 MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK ...
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V TIMING CHARACTERISTICS Parameter MPU PORT SCLOCK Frequency SCLOCK High Pulsewidth SCLOCK Low Pulsewidth Hold Time (Start Condition Setup Time (Start Condition Data Setup Time SDATA, SCLOCK Rise Time, ...
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ADV7194 SDA SCL CLOCK HSYNC, CONTROL VSYNC, I/PS BLANK PIXEL INPUT DATA HSYNC, VSYNC, CONTROL BLANK, O/PS CSO_HSO, VSO, CLAMP TTXREQ t 16 CLOCK TTX 4 CLOCK CYCLES CLOCK Y0 – Y9 INCLUDING SYNC INFORMATION Cb0 ...
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... Y[7]/P17 Y[8]/P18 Y[9]/P19 Model Temperature Range ADV7194KST 0°C to 70°C CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7194 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges ...
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ADV7194 Pin Input/ No. Mnemonic Output 1–10 P0–P9 I 11–20 Y0/P10–Y9/P19 I 21, 34, 68 22, 33, 43, 69, DGND G 80 HSYNC 23 I/O VSYNC 24 I/O BLANK 25 I/O 26–31, 75–78 Cb0–Cb9 I 32 ...
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GENERAL DESCRIPTION The ADV7194 is an integrated Digital Video Encoder that con- verts digital CCIR-601/656 4:2:2 10-bit (or 20-bit or 8-/16-bit) component video data into a standard analog baseband television signal compatible with worldwide standards. Additionally there is the possibility ...
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ADV7194 Digital noise reduction allows improved picture quality in removing low-amplitude, high-frequency noise. Figure 6 shows the DNR functionality in the two modes available. Programmable gamma correction is also available. The figure below shows the response of different gamma values ...
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When used to interface progressive scan systems, the ADV7194 allows input to YCrCb signals in Progressive Scan format (3 × 10 bit) before these signals are routed to the interpolation filters and the DACs. INTERNAL FILTER RESPONSE The Y Filter ...
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ADV7194 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 –70 0 ...
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FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 –70 ...
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ADV7194 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 – FREQUENCY – MHz 0 –10 –20 –30 –40 –50 –60 –70 0 ...
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FEATURES—FUNCTIONAL DESCRIPTION BLACK BURST OUTPUT It is possible to output a black burst signal from two DACs. This signal output is very useful for professional video equipment since it enables two video sources to be locked together. (Mode Register 9.) ...
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ADV7194 UNDERSHOOT LIMITER A limiter is placed after the digital filters. This prevents any synchronization problems for TVs. The level of undershoot is programmable between –1.5 IRE, –6 IRE, –11 IRE when oper- ating in 4× Oversampling Mode. In 2× ...
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ADV7194 54MHz PLL 27MHz MPEG2 ENCODER PIXEL BUS CORE PROGRESSIVE SCAN 30-BIT INTERFACE DECODER The progressive scan decoder deinterlaces the data from the MPEG2 decoder. This now means that there are 525 video lines per field in NTSC mode and ...
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ADV7194 YUV LEVELS This functionality allows the ADV7194 to output SMPTE levels or Betacam levels on the Y output when configured in PAL or NTSC mode. Sync Betacam 286 mV SMPTE 300 mV MII 300 mV As the data path ...
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RESET DAC D, XXXXXXX DAC E DAC F XXXXXXX DAC A, XXXXXXX DAC B, DAC C MR26 XXXXXXX PIXEL_DATA_VALID DIGITAL TIMING XXXXXXX COMPOSITE VIDEO VIDEO DECODER e.g., VCR ADV7185 OR CABLE H/L TRANSITION COUNT START LOW 14 BITS 128 RESERVED ...
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ADV7194 Mode 0 (CCIR–656): Slave Option (Timing Register 0 TR0 = The ADV7194 is controlled by the SAV (Start Active Video) and EAV (End Active Video) Time Codes in the Pixel Data. ...
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DISPLAY 622 623 624 625 EVEN FIELD ODD FIELD DISPLAY 309 310 311 312 313 314 H V ODD FIELD F EVEN FIELD ANALOG VIDEO VERTICAL BLANK ...
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ADV7194 Mode 1: Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7194 accepts Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when ...
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Mode 1: Master Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7194 can generate Horizontal SYNC and Odd/Even FIELD signals. A transition of the FIELD input when ...
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ADV7194 DISPLAY 622 623 624 625 HSYNC BLANK VSYNC EVEN FIELD DISPLAY 309 310 311 312 HSYNC BLANK VSYNC ODD FIELD Mode 2: Master Option HSYNC, VSYNC, BLANK (Timing Register 0 TR0 = ...
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Mode 3: Master/Slave Option HSYNC, BLANK, FIELD (Timing Register 0 TR0 = this mode the ADV7194 accepts or generates Horizontal SYNC and ...
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ADV7194 MPU PORT DESCRIPTION The ADV7194 supports a 2-wire serial (I processor bus driving multiple peripherals. Two inputs Serial Data (SDA) and Serial Clock (SCL) carry information between any device connected to the bus. Each slave device is recog- nized ...
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REGISTER ACCESSES The MPU can write to or read from all of the registers of the ADV7194 except the Subaddress Registers which are write only registers. The Subaddress Register determines which register the next read or write operation accesses. All ...
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ADV7194 MODE REGISTER 0 MR0 (MR07–MR00) (Address (SR4–SR0) = 00H) Figure 55 shows the various operations under the control of Mode Register 0. MR0 BIT DESCRIPTION Output Video Standard Selection (MR00–MR01) These bits are used to setup the encoder mode. ...
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MODE REGISTER 2 MR2 (MR27–MR20) (Address (SR4–SR0) = 02H) Mode Register 8-bit-wide register. Figure 57 shows the various operations under the control of Mode Register 2. MR2 BIT DESCRIPTION RGB/YUV Control (MR20) This bit enables the output ...
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ADV7194 MODE REGISTER 3 MR3 (MR37–MR30) (Address (SR4–SR0) = 03H) Mode Register 8-bit-wide register. Figure 58 shows the various operations under the control of Mode Register 3. MR3 BIT DESCRIPTION Revision Code (MR30–MR31) This bit is read ...
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MR47 COLOR BAR CONTROL MR46 0 DISABLE 1 ENABLE INTERLACED MODE CONTROL MR47 0 INTERLACED 1 NONINTERLACED MODE REGISTER 5 MR5 (MR57–MR50) (Address (SR4–SR0) = 05H) Mode Register 8-bit-wide register. Figure 60 shows the various operations under ...
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ADV7194 MR67 MR66 MR67 MR66 MR65 FIELD COUNTER MODE REGISTER 6 MR6 (MR67–MR60) (ADDRESS (SR4–SR0) = 06H) Mode Register 8-bit-wide register. Figure 61 shows the various operations under the control of Mode Register 6. MR6 BIT DESCRIPTION ...
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MR87 GAMMA ENABLE CONTROL MR86 0 1 GAMMA CURVE SELECT CONTROL MR87 0 CURVE A 1 CURVE B MODE REGISTER 8 MR8 (MR87–MR80) (Address (SR4–SR0) = 08H) Mode Register 8-bit-wide register. Figure 63 shows the various operations ...
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ADV7194 MR97 MR96 MR97 MR96 ZERO MUST MR95 MR94 BE WRITTEN TO THESE BITS Chroma Delay Control (MR95–MR97) The Chroma signal can be delayed eight clock cycles at 27 MHz using MR94–95. For further information see also ...
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TR17 TR16 HSYNC TO PIXEL DATA ADJUST TR17 TR16 TIMING MODE 1 (MASTER/PAL) HSYNC VSYNC SUBCARRIER FREQUENCY REGISTERS 3–0 (FSC31–FSC0) (Address (SR4–SR0) = 0CH–0FH) These 8-bit-wide registers are ...
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ADV7194 LINE 17 LINE 16 LINE 15 LINE 14 LINE 13 LINE 12 LINE 11 LINE 10 FIELD 1/3 PCO7 PCO6 PCO5 PCO4 PCO3 LINE 25 LINE 24 LINE 23 LINE 22 LINE 21 LINE 20 FIELD 1/3 PCO15 PCO14 ...
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CGMS_WSS REGISTER 1 C/W1 (C/W17–C/W10) (Address (SR4–SR0) = 1AH) CGMS_WSS register 8-bit-wide register. Figure 76 shows the operations under control of this register. C/W1 BIT DESCRIPTION CGMS/WSS Data (C/W10–C/W15) These bit locations are shared by CGMS data ...
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ADV7194 HUE ADJUST CONTROL REGISTER (HCR) (Address (SR5–SR0) = 20H) The hue control register is an 8-bit-wide register used to adjust the hue on the composite and chroma outputs. Figure 80 shows the operation under control of this register. HCR7 ...
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SHARPNESS RESPONSE REGISTER (PR) (Address (SR5–SR0) = 22H) The sharpness response register is an 8-bit-wide register. The four MSBs are set to 0. The four LSBs are written to in order to select a desired filter response. Figure 82 shows ...
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ADV7194 DNR17 BLOCK SIZE CONTROL DNR17 0 8 PIXELS 1 16 PIXELS DNR2 BIT DESCRIPTION DNR Input Select (DNR20–DNR22) Three bits are assigned to select the filter which is applied to the incoming Y data. The signal which lies in ...
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DNR27 DNR26 BLOCK OFFSET CONTROL DNR DNR DNR DNR • • • • • • • • • GAMMA ...
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ADV7194 BRIGHTNESS DETECT REGISTER (Address (SR5–SR0) = 34H) The Brightness Detect Register is an 8-bit-wide register used only to read back data in order to monitor the brightness/darkness of the incoming video data on a field-by-field basis. The brightness 2 ...
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BOARD DESIGN AND LAYOUT CONSIDERATIONS The ADV7194 is a highly integrated circuit containing both precision analog and high-speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high-speed digital circuitry. ...
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ADV7194 UNUSED INPUTS SHOULD BE GROUNDED 4.7k 4.7 F 6.3V 27MHz CLOCK (SAME CLOCK AS USED BY MPEG2 5V (V DECODER) POWER SUPPLY DECOUPLING FOR EACH POWER SUPPLY GROUP 10nF ...
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The ADV7194 supports closed captioning conforming to the standard television synchronizing waveform for color transmis- sion. Closed captioning is transmitted during the blanked active line time of Line 21 of the odd fields and Line 284 of even fields. Closed ...
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ADV7194 COPY GENERATION MANAGEMENT SYSTEM (CGMS) The ADV7194 supports Copy Generation Management System (CGMS) conforming to the standard. CGMS data is transmit- ted on Line 20 of the odd fields and Line 283 of even fields. Bits C/W05 and C/W06 ...
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The ADV7194 supports Wide Screen Signalling (WSS) conform- ing to the standard. WSS data is transmitted on Line 23. WSS data can only be transmitted when the ADV7194 is configured in PAL mode. The WSS data is 14 bits long, ...
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ADV7194 Time the time needed by the ADV7194 to interpolate PD input data on TTX and insert it onto the CVBS or Y outputs, = 10.2 µs after the leading edge of such that it appears T ...
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If an output filter is required for the CVBS, Y, UV, Chroma and RGB outputs of the ADV7194, the following filter in Figure 100 can be used in 2× Oversampling Mode. In 4× Oversampling Mode the filter in Figure 102 ...
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ADV7194 External buffering is needed on the ADV7194 DAC outputs. The configuration in Figure 105 is recommended. When calculating absolute output full-scale current and voltage use the following equations: × OUT OUT LOAD × K)/R I ...
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The ADV7194 registers can be set depending on the user standard required. The following examples give the various register for- mats for several video standards. NTSC (F = 3.5795454 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 ...
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ADV7194 PAL 4.43361875 MHz) SC Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode Register ...
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POWER-ON RESET REG VALUES (PAL_NTSC = 0, NTSC Selected) Address 00Hex Mode Register 0 01Hex Mode Register 1 02Hex Mode Register 2 03Hex Mode Register 3 04Hex Mode Register 4 05Hex Mode Register 5 06Hex Mode Register 6 07Hex Mode ...
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ADV7194 130.8 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 100 IRE 7.5 IRE 0 IRE –40 IRE 963.8mV 286mV (pk-pk) 650mV 335.2mV 0mV 100 IRE 7.5 IRE 0 IRE –40 IRE APPENDIX 9 NTSC WAVEFORMS (WITH PEDESTAL) 629.7mV ...
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NTSC WAVEFORMS (WITHOUT PEDESTAL) 130.8 IRE 100 IRE 0 IRE –40 IRE 100 IRE 0 IRE –40 IRE 978mV 286mV (pk-pk) 650mV 283mV 0mV 100 IRE 0 IRE –40 IRE ADV7194 1289.8mV PEAK COMPOSITE REF WHITE 1052.2mV 714.2mV BLANK/BLACK LEVEL ...
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ADV7194 1284.2mV 1047.1mV 350.7mV 50.8mV 1047mV 350.7mV 50.8mV 990mV 300mV (pk-pk) 650mV 318mV 0mV 1050.2mV 351.8mV 51mV PAL WAVEFORMS PEAK COMPOSITE 696.4mV BLANK/BLACK LEVEL 696.4mV BLANK/BLACK LEVEL 672mV (pk-pk) 698.4mV BLANK/BLACK LEVEL REF WHITE SYNC LEVEL REF WHITE SYNC LEVEL ...
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PARADE SMPTE/EBU PAL Y(A) Pb( 250 700 200 600 150 500 400 100 300 50 200 0 100 –50 0 –100 100 –150 200 –200 300 –250 mV GREEN (A) mV BLUE (B) 700 700 600 600 500 ...
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ADV7194 334mV 171mV BETACAM LEVEL 0mV 171mV 334mV 505mV 309mV 158mV BETACAM LEVEL 0mV –158mV –309mV –467mV 232mV SMPTE LEVEL 118mV 0mV –118mV –232mV –350mV UV WAVEFORMS 505mV BETACAM LEVEL 0mV 0mV 467mV BETACAM LEVEL 0mV 0mV 350mV SMPTE LEVEL ...
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OUTPUT WAVEFORMS 0.6 0.4 0.2 0.0 0.2 L608 0.0 10.0 20.0 NOISE REDUCTION: 0.00 dB APL = 39.1% 625 LINE PAL NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.5 0.0 L575 0.0 10.0 20.0 APL NEEDS SYNC ...
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ADV7194 0.5 0.0 –0.5 L575 10.0 APL NEEDS SYNC = SOURCE! 625 LINE PAL SLOW CLAMP TO 0. 6.72 s 100.0 0.5 50.0 0.0 0.0 –50.0 0.0 APL = 44.6% 525 LINE NTSC SLOW CLAMP TO 0.00 V ...
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F2 L238 10.0 20.0 NOISE REDUCTION: 15.05dB APL = 44.7% 525 LINE NTSC NO FILTERING SLOW CLAMP TO 0. 6.72 s 0.4 50.0 0.2 0.0 –0.2 –50.0 –0.4 F1 L76 ...
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ADV7194 COLOR BAR (NTSC) FIELD = 1 LINE = 21 LUMINANCE LEVEL (IRE) 99.6 69.0 100 50 0 GRAY YELLOW CHROMINANCE LEVEL (IRE) 0.0 62.1 100 50 0 GRAY YELLOW CHROMINANCE PHASE (DEGREE) 167.3 400 200 0 GRAY YELLOW AVERAGE ...
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DG DP (NTSC) WFM FIELD = 1, LINE = 21 DIIFFERENTIAL GAIN (PERCENT) MIN = 0.00, MAX = 0.27, p-p/MAX = 0.27 0.00 0.21 0.02 0.07 2.5 1.5 0.5 –0.5 –1.5 –2 ...
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ADV7194 CHROMINANCE NONLINEARITY(NTSC) WFM FIELD = 2, LINE = 217 CHROMINANCE AMPLITUDE ERROR (PERCENT) 0.5 0 –10 20IRE 40IRE CHROMINANCE PHASE ERROR (DEGREE) –0.0 0 –5 20IRE 40IRE CHROMINANCE LUMINANCE INTERMODULATION (PERCENT OF 714mV) 0.0 0.1 ...
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NOISE SPECTRUM (NTSC) WFM FIELD = 2, LINE = 223 AMPLITUDE (0dB = 714mV p-p) BANDWIDTH 10kHz TO FULL 20 0 –20 –40 –60 –80 –100 MHz NOISE SPECTRUM (NTSC) WFM FIELD = 2, LINE = 217 ...
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ADV7194 APL = 39. SOUND IN SYNC OFF APL = 45.1% YI –Q SETUP 7.5% APPENDIX 10 VECTOR PLOTS 75% 100 R ...
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OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 80-Lead LQFP (ST-80) 0.640 (16.25) SQ 0.620 (15.75) 0.063 (1.60) 0.553 (14.05) MAX SQ 0.549 (13.95) 0.030 (0.75) 80 0.020 (0.50) 1 SEATING PLANE TOP VIEW (PINS DOWN) 0.004 (0.10) 20 MAX ...