ADV7181BBCPZ Analog Devices Inc, ADV7181BBCPZ Datasheet - Page 47

IC ENCODER SDTV MULTI 64-LFCSP

ADV7181BBCPZ

Manufacturer Part Number
ADV7181BBCPZ
Description
IC ENCODER SDTV MULTI 64-LFCSP
Manufacturer
Analog Devices Inc
Type
Video Decoderr
Datasheet

Specifications of ADV7181BBCPZ

Applications
Recorders, Set-Top Boxes
Voltage - Supply, Analog
3.15 V ~ 3.45 V
Voltage - Supply, Digital
1.65 V ~ 2 V
Mounting Type
Surface Mount
Package / Case
64-LFCSP
Resolution (bits)
9bit
Input Format
Analog
Output Format
Digital
Adc Sample Rate
54MSPS
No. Of Input Channels
6
Supply Voltage Range
3V To 3.6V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
EVAL-ADV7181BEB - BOARD EVALUATION FOR ADV7181
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ADV7181BBCPZ
Manufacturer:
ADI/亚德诺
Quantity:
20 000
The closed captioning data (CCAP) is available in the I
registers, and is also inserted into the output video data stream
during horizontal blanking.
The Gemstar-compatible data is not available in the I
registers, and is inserted into the data stream only during
horizontal blanking.
WSSD Wide Screen Signaling Detected, Address 0x90[0]
Logic 1 for this bit indicates the data in the WSS1 and WSS2
registers is valid.
The WSSD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When WSSD is 0, no WSS is detected and confidence in the
decoded data is low.
When WSSD is 1, WSS is detected and confidence in the
decoded data is high.
CCAPD Closed Caption Detected, Address 0x90[1]
Logic 1 for this bit indicates the data in the CCAP1 and CCAP2
registers is valid.
The CCAPD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When CCAPD is 0, no CCAP signals are detected and
confidence in the decoded data is low.
When CCAPD is 1, the CCAP sequence is detected and
confidence in the decoded data is high.
EDTVD EDTV Sequence Detected, Address 0x90[2]
Logic 1 for this bit indicates the data in the EDTV1, 2, 3
registers is valid.
The EDTVD bit goes high if the rising edge of the start bit is
detected within a time window, and if the polarity of the parity
bit matches the transmitted data.
When EDTVD is 0, no EDTV sequence is detected. Confidence
in decoded data is low.
When EDTVD is 1, an EDTV sequence is detected. Confidence
in decoded data is high.
11.0μs
SEQUENCE
RUN-IN
START
CODE
2
C
38.4μs
42.5μs
2
0
C
Figure 30. WSS Data Extraction
1
Rev. B | Page 47 of 100
2
WSS1[7:0]
3
4
5
6
CGMSD CGMS-A Sequence Detected, Address 0x90[3]
Logic 1 for this bit indicates the data in the CGMS1, 2, 3
registers is valid. The CGMSD bit goes high if a valid CRC
checksum has been calculated from a received CGMS packet.
When CGMSD is 0, no CGMS transmission is detected and
confidence in decoded data is low.
When CGMSD is 1, the CGMS sequence is decoded and
confidence in decoded data is high.
CRC_ENABLE CRC CGMS-A Sequence, Address 0xB2[2]
For certain video sources, the CRC data bits can have an invalid
format. In such circumstances, the CRC checksum validation
procedure can be disabled. The CGMSD bit goes high if the
rising edge of the start bit is detected within a time window.
When CRC_ENABLE is 0, no CRC check is performed. The
CGMSD bit goes high if the rising edge of the start bit is
detected within a time window.
When CRC_ENABLE is 1 (default), CRC checksum is used to
validate the CGMS sequence. The CGMSD bit goes high for a
valid checksum. ADI recommended setting.
Wide Screen Signaling Data
WSS1[7:0], Address 0x91[7:0],
WSS2[7:0], Address 0x92[7:0]
Figure 30 shows the bit correspondence between the analog
video waveform and the WSS1/WSS2 registers. WSS2[7:6] are
undetermined and should be masked out by software.
EDTV Data Registers
EDTV1[7:0], Address 0x93[7:0],
EDTV2[7:0], Address 0x94[7:0],
EDTV3[7:0], Address 0x95[7:0]
Figure 31 shows the bit correspondence between the analog
video waveform and the EDTV1/EDTV2/EDTV3 registers.
EDTV3[7:6] are undetermined and should be masked out by
software. EDTV3[5] is reserved for future use and, for now,
contains a 0. The three LSBs of the EDTV waveform are
currently not supported.
7
0
1
WSS2[5:0]
2
3
4
5
ACTIVE
VIDEO
ADV7181B

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