LTC1069-6IS8 Linear Technology, LTC1069-6IS8 Datasheet - Page 6

• Manufacturer Part Number: LTC1069-6IS8
• Description: IC FILTR 8TH ORDER LOWPASS 8SOIC
• Manufacturer: Linear Technology

Specifications of LTC1069-6IS8

• Filter Type: Elliptic, Lowpass Switched Capacitor
• Frequency - Cutoff Or Center: 14kHz/20kHz
• Number Of Filters: 1
• Max-order: 8th
• Voltage - Supply: 3 V ~ 10 V, ±1.5 V ~ 5 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

PIN FUNCTIONS
LTC1069-6
for single supply operation, the internal biasing of Pin 1
allows optimum output swing. The AGND pin should be
buffered if used to bias other ICs. Figure 2 shows the
connections for single supply operation.
V
and the V
0.1μF capacitor to an adequate analog ground. The fi lter’s
power supplies should be isolated from other digital or
high voltage analog supplies. A low noise linear supply is
recommended. Switching power supplies will lower the
signal-to-noise ratio of the fi lter. Unlike previous monolithic
fi lters, the power supplies can be applied in any order, that
is, the positive supply can be applied before the negative
supply and vice versa. Figure 3 shows the connection for
dual supply operation.
6
+
, V
–
Figure 2. Connections for Single Supply Operation
Figure 3. Connections for Dual Supply Operation
(Pins 2, 7): Power Supply Pins. The V
–
(Pin 7, if used) should be bypassed with a
STAR
SYSTEM
GROUND
STAR
SYSTEM
GROUND
V
0.1μF
0.1μF
V
+
V
IN
IN
0.47μF
V
ANALOG GROUND PLANE
+
ANALOG GROUND PLANE
1
2
3
4
1
2
3
4
GROUND
DIGITAL
GROUND
DIGITAL
PLANE
PLANE
AGND
V
NC
V
AGND
V
NC
V
+
IN
IN
+
LTC1069-6
LTC1069-6
V
V
CLK
CLK
OUT
OUT
NC
NC
V
V
–
–
SOURCE
SOURCE
CLOCK
8
7
6
5
CLOCK
8
7
6
5
V
V
1k
1k
OUT
OUT
1069-6 F02
1069-6 F03
0.1μF
V
–
+
(Pin 2)
NC (Pins 3, 6): No Connection. Pins 3 and 6 are not
connected to any internal circuitry; they should be tied
to ground.
V
connected to the inverting input of an op amp through a
50k resistor.
CLK (Pin 5): Clock Input Pin. Any TTL or CMOS clock
source with a square wave output and 50% duty cycle
(±10%) is an adequate clock source for the device. The
power supply for the clock source should not necessarily
be the fi lter’s power supply. The analog ground of the fi lter
should be connected to the clock’s ground at a single
point only. Table 1 shows the clock’s low and high level
threshold value for a dual or single supply operation. A
pulse generator can be used as a clock source provided
the high level ON time is greater than 0.42μs (V
Sine waves less than 100kHz are not recommended for
clock frequencies because, excessive slow clock rise or
fall times generate internal clock jitter. The maximum clock
rise or fall time is 1μs. The clock signal should be routed
from the right side of the IC package to avoid coupling
into any input or output analog signal path. A 1k resistor
between the clock source and the Clock Input (Pin 5) will
slow down the rise and fall times of the clock to further
reduce charge coupling (Figure 1).
Table 1. Clock Source High and Low Thresholds
POWER SUPPLY
Dual Supply = ±5V
Single Supply = 10V
Single Supply = 5V
Single Supply = 3.3V
V
fi lter, and it can source 8mA or sink 1mA. The total harmonic
distortion of the fi lter will degrade when driving coaxial
cables or loads less than 20k without an output buffer.
IN
OUT
(Pin 4): Filter Input Pin. The Filter Input pin is internally
(Pin 8): Filter Output Pin. Pin 8 is the output of the
HIGH LEVEL
1.5V
6.5V
1.5V
1.2V
LOW LEVEL
0.5V
5.5V
0.5V
0.5V
S
= ±5V).
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