MAX7315ATE+ Maxim Integrated Products, MAX7315ATE+ Datasheet - Page 8

• Manufacturer Part Number: MAX7315ATE+
• Description: IC I/O EXPANDER I2C 8B 16TQFN-EP
• Manufacturer: Maxim Integrated Products

Specifications of MAX7315ATE+

• Interface: I²C, SMBus
• Number Of I /o: 8
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 2 V ~ 3.6 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-TQFN Exposed Pad
• Operating Supply Voltage: 2 V to 3.6 V
• Power Dissipation: 1176 mW
• Operating Temperature Range: - 40 C to + 125 C
• Input Voltage: 1.08 V to 1.4 V
• Maximum Clock Frequency: 400 KHz
• Mounting Style: SMD/SMT
• Output Voltage: 0.15 V
• Chip Configuration: 8 Bit
• Bus Frequency: 400kHz
• Ic Interface Type: I2C, SMBus
• No. Of I/o's: 8
• Supply Voltage Range: 2V To 3.6V
• Digital Ic Case Style: TQFN
• No. Of Pins: 16
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8-Port I/O Expander with LED Intensity
Control, Interrupt, and Hot-Insertion Protection
only as an input. A pullup resistor, typically 4.7kΩ, is
required on SCL if there are multiple masters on the 2-
wire interface, or if the master in a single-master system
has an open-drain SCL output.
Each transmission consists of a START condition
(Figure 3) sent by a master, followed by the MAX7315
7-bit slave address plus R/W bit, a register address
byte, one or more data bytes, and finally a STOP condi-
tion (Figure 3).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
Figure 3. Start and Stop Conditions
Figure 4. Bit Transfer
Figure 5. Acknowledge
Figure 6. Slave Address
8
SDA
SCL
SDA
SCL
TRANSMITTER
_______________________________________________________________________________________
CONDITION
RECEIVER
START
SDA BY
SDA BY
SDA
SCL
S
SCL
DATA LINE STABLE;
CONDITION
START
DATA VALID
S
MSB
A6
1
CHANGE OF DATA
ALLOWED
A5
Start and Stop Conditions
2
FOR ACKNOWLEDGE
A4
CLOCK PULSE
8
CONDITION
A3
9
STOP
P
A2
from high to low while SCL is high. When the master
has finished communicating with the slave, it issues a
STOP (P) condition by transitioning SDA from low to
high while SCL is high. The bus is then free for another
transmission (Figure 3).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 4).
The acknowledge bit is a clocked 9th bit that the recipi-
ent uses to handshake receipt of each byte of data
(Figure 5). Thus, each byte transferred effectively
requires 9 bits. The master generates the 9th clock
pulse, and the recipient pulls down SDA during the
acknowledge clock pulse so the SDA line is stable low
during the high period of the clock pulse. When the
master is transmitting to the MAX7315, the device gen-
erates the acknowledge bit because the MAX7315 is
the recipient. When the MAX7315 is transmitting to the
master, the master generates the acknowledge bit
because the master is the recipient.
The MAX7315 has a 7-bit long slave address (Figure 6).
The eighth bit following the 7-bit slave address is the
R/W bit. The R/W bit is low for a write command, high
for a read command.
The slave address bits A6 through A0 are selected by
the address inputs AD0, AD1, and AD2. These pins can
be connected to GND, V+, SDA, or SCL. The MAX7315
has 64 possible slave addresses (Table 1) and, there-
fore, a maximum of 64 MAX7315 devices can be con-
trolled independently from the same interface.
A write to the MAX7315 comprises the transmission of
the MAX7315’s slave address with the R/W bit set to
zero, followed by at least 1 byte of information. The first
byte of information is the command byte. The command
byte determines which register of the MAX7315 is to be
written to by the next byte, if received (Table 2). If a
STOP condition is detected after the command byte is
received, then the MAX7315 takes no further action
beyond storing the command byte.
A1
Message Format for Writing the MAX7315
LSB
A0
R/W
Slave Address
ACK
Acknowledge
Bit Transfer