MAX7323AEE+T Maxim Integrated Products, MAX7323AEE+T Datasheet - Page 9

• Manufacturer Part Number: MAX7323AEE+T
• Description: IC I/O EXPANDER I2C 4B 16QSOP
• Manufacturer: Maxim Integrated Products

Specifications of MAX7323AEE+T

• Interface: I²C
• Number Of I /o: 4
• Interrupt Output: Yes
• Frequency - Clock: 400kHz
• Voltage - Supply: 1.71 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 16-QSOP
• Includes: POR
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX7323 operates as a slave that sends and
receives data through an I
uses a serial data line (SDA) and a serial clock line (SCL)
to achieve bidirectional communication between
master(s) and slave(s). The master initiates all data trans-
fers to and from the MAX7323 and generates the SCL
clock that synchronizes the data transfer (Figure 1).
SDA operates as both an input and an open-drain out-
put. A pullup resistor, typically 4.7kΩ, is required on
SDA. SCL operates only as an input. A pullup resistor,
typically 4.7kΩ, is required on SCL if there are multiple
masters on the 2-wire interface, or if the master in a sin-
gle-master system has an open-drain SCL output.
Each transmission consists of a START condition sent
by a master, followed by the MAX7323’s 7-bit slave
address plus R/W bit, 1 or more data bytes, and finally
a STOP condition (Figure 2).
Both SCL and SDA remain high when the interface is
not busy. A master signals the beginning of a transmis-
sion with a START (S) condition by transitioning SDA
from high to low while SCL is high. When the master
has finished communicating with the slave, the master
issues a STOP (P) condition by transitioning SDA from
low to high while SCL is high. The bus is then free for
another transmission (Figure 2).
One data bit is transferred during each clock pulse.
The data on SDA must remain stable while SCL is high
(Figure 3).
Figure 1. 2-Wire Serial Interface Timing Details
SDA
SCL
t
HD,STA
START CONDITION
I
2
C Port Expander with 4 Push-Pull Outputs
_______________________________________________________________________________________
t
LOW
START and STOP Conditions
2
t
R
C interface. The interface
t
SU,DAT
t
HIGH
Serial Interface
t
F
Serial Addressing
t
HD,DAT
Bit Transfer
t
REPEATED START CONDITION
SU,STA
The acknowledge bit is a clocked 9th bit the recipient
uses to acknowledge receipt of each byte of data
(Figure 4). Each byte transferred effectively requires 9
bits. The master generates the 9th clock pulse, and the
recipient pulls down SDA during the acknowledge
clock pulse, such that the SDA line is stable low during
the high period of the clock pulse. When the master is
transmitting to the MAX7323, the device generates the
acknowledge bit because the MAX7323 is the recipient.
When the MAX7323 is transmitting to the master, the
master generates the acknowledge bit because the
master is the recipient.
The MAX7323 has a 7-bit-long slave address (Figure
5). The 8th bit following the 7-bit slave address is the
R/W bit. It is low for a write command, and high for a
read command.
The first (A6), second (A5), and third (A4) bits of the
MAX7323 slave address are always 1, 1, and 0.
Connect AD2 and AD0 to GND, V+
select slave address bits A3, A2, A1, and A0. The
MAX7323 has 16 possible slave addresses (Table 3),
allowing up to 16 MAX7323 devices on an I
Figure 2. START and STOP Conditions
SDA
SCL
and 4 Open-Drain I/Os
CONDITION
START
S
t
HD,STA
t
SU,STO
CONDITION
STOP
,
t
SDA, or SCL to
BUF
Slave Address
Acknowledge
CONDITION
2
START
C bus.
CONDITION
STOP
P
9