MAX7301ATL+T Maxim Integrated Products, MAX7301ATL+T Datasheet - Page 7

• Manufacturer Part Number: MAX7301ATL+T
• Description: IC I/O EXPANDER SPI 28B 40TQFN
• Manufacturer: Maxim Integrated Products

Specifications of MAX7301ATL+T

• Interface: SPI/QSPI™/MICROWIRE™
• Number Of I /o: 28
• Interrupt Output: Yes
• Frequency - Clock: 26MHz
• Voltage - Supply: 2.5 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 40-TQFN Exposed Pad
• Package: 40TQFN EP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

The MAX7301 is written to using the following
sequence:
1) Take SCLK low.
2) Take CS low. This enables the internal 16-bit shift
3) Clock 16 bits of data into DIN—D15 first, D0 last—
4) Take CS high (either while SCLK is still high after
5) Take SCLK low (if not already low).
Figure 4 shows a write operation when 16 bits are
transmitted.
It is acceptable to clock more than 16 bits into the
MAX7301 between taking CS low and taking CS high
again. In this case, only the last 16 bits clocked into the
MAX7301 are retained.
Figure 1. MAX7301 Functional Diagram
register.
observing the setup and hold times (bit D15 is low,
indicating a write command).
clocking in the last data bit, or after taking SCLK
low).
P4 TO P31
4-Wire-Interfaced, 2.5V to 5.5V, 20-Port and
SCLK
DIN
CS
_______________________________________________________________________________________
D0
D0
GPIO DATA
D1
D1
8
GPIO
D2
D2
CONFIGURATION
D3
D3
DATA BYTE
R/W
8
D4
D4
D5
D5
D6
D6
D7
D7
PORT CHANGE
DETECTOR
Any register data within the MAX7301 may be read by
sending a logic high to bit D15. The sequence is:
1) Take SCLK low.
2) Take CS low (this enables the internal 16-bit Shift
3) Clock 16 bits of data into DIN—D15 first to D0 last.
4) Take CS high (either while SCLK is still high after
5) Take SCLK low (if not already low).
6) Issue another read or write command (which can
D8
D8
register).
D15 is high, indicating a read command and bits
D14 through D8 containing the address of the regis-
ter to be read. Bits D7–D0 contain dummy data,
which is discarded.
clocking in the last data bit, or after taking SCLK
low), positions D7 through D0 in the Shift register
are now loaded with the register data addressed by
bits D1 through D8.
be a No-Op), and examine the bit stream at DOUT;
the second 8 bits are the contents of the register
addressed by bits D1 through D8 in step 3.
D9
D9
28-Port I/O Expander
D10
D10
COMMAND BYTE
D11
D11
D12
D12
REGISTER DECODE
DATA
COMMAND
PORT REGISTERS
8
MASK REGISTER
CONFIGURATION
Reading Device Registers
D13
D13
8
REGISTERS
CE
D14
D14
R/W
D15
D15
DOUT
7