SI3008-B-FS Silicon Laboratories Inc, SI3008-B-FS Datasheet - Page 17

• Manufacturer Part Number: SI3008-B-FS
• Description: IC ISOMODEM FCC LINE-SIDE 8SOIC
• Manufacturer: Silicon Laboratories Inc

Specifications of SI3008-B-FS

• Data Format: V.22, V23, V.32, V.34, V.90, Bell 103, Bell 212A
• Baud Rates: 56k
• Interface: Parallel
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Product: Modem Module
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2.9. Clock Generation Subsystem
The Si3000 contains an on-chip clock generator. Using
a single MCLK input frequency, the Si3000 can
generate all the desired standard modem sample rates,
as well as the common 11.025 kHz rate for audio
playback.
The clock generator consists of a phase-locked loop
(PLL1) that achieves the desired sample frequency.
Figure 18
architecture of the PLL allows for fast lock time on initial
start-up, fast lock time when changing modem sample
rates and high noise immunity. A large number of MCLK
frequencies between 1 MHz and 60 MHz are supported.
2.9.1. Programming the Clock Generator
As noted in Figure 18, the clock generator must output a
clock equal to 1024*Fs, where Fs is the desired sample
rate. The 1024*Fs clock is determined through
programming of the following registers:
N1 (register 3) and M1 (register 4) are 8-bit unsigned
values. F
Table 12 lists several standard crystal rates that could
be supplied to MCLK.
When programming the registers of the clock generator,
the order of register writes is important. For PLL
updates, N1 (register 3) must always be written first,
immediately followed by a write to M1 (register 4).
Note: The values shown in Table 12 satisfy the equations
Register 3 - N1 divider, 8 bits.
Register 4 - M1 divider, 8 bits
above. However, when programming the registers for
N1 and M1, the value placed in these registers must be
one less than the value calculated from the equations.
MCLK
illustrates
M CLK
is the clock provided to the MCLK pin.
÷ N1
the
Figure 18. Clock Generation Subsystem (PLL)
clock
P
D
F
U P1
generator.
8 bits
÷ M 1
V CO1
The
Rev. 1.4
Table 12. MCLK Examples for 8 kHz
*Note: S ee P LL bit in Register 2.
÷ 5 or
÷ 10*
F
MCLK (MHz)
PLL1
10.0800
10.5600
14.7456
16.0000
18.4320
24.5760
25.8048
33.7600
44.2368
46.0800
47.9232
48.0000
56.0000
11.0592
1.8432
4.0000
4.0960
5.2800
5.7600
6.1440
8.1920
9.2160
12.288
59.200
1024·Fs
175
185
211
117
N1
25
33
63
33
27
25
63
27
75
9
1
9
3
1
9
3
9
9
3
9
200
256
256
256
128
100
100
256
100
128
128
M1
10
64
20
40
10
25
64
20
25
64
Si3000
5
5
8
17