SI3050-E-FM Silicon Laboratories Inc, SI3050-E-FM Datasheet
SI3050-E-FM
Specifications of SI3050-E-FM
Related parts for SI3050-E-FM
SI3050-E-FM Summary of contents
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... The Voice DAA is available as a chipset, a system-side device (Si3050) paired with a line-side device (Si3011/18/19). The Si3050 is available in a 20-pin TSSOP or a 24-pin QFN. The Si3011/18/19 is available in a 16-pin TSSOP, a 16-pin SOIC 20-pin QFN and requires minimal external components ...
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... Si3050 + Si3011/18/19 2 Rev. 1.4 ...
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... Gain Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 5.28. Transhybrid Balance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 5.29. Filter Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.30. Clock Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 5.31. Communication Interface Mode Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 5.32. PCM Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 5.33. Companding in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.34. 16 kHz Sampling Operation in PCM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 5.35. SPI Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 5.36. GCI Highway . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Si3050 + Si3011/18/19 Rev. 1.4 Page 3 ...
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... PCB Land Pattern: Si3011/18/19 SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 14. Package Outline: 16-Pin TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118 14.1. PCB Land Pattern: Si3011/18/19 TSSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120 15. Package Outline: 20-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .121 16. PCB Land Pattern: Si3011/18/19 QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Silicon Labs Si3050 Support Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127 Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 4 Rev. 1.4 ...
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... Notes: 1. The Si3050 specifications are guaranteed when the typical application circuit (including component tolerance) and any Si3050 and any Si3011/18/19 are used. See "2. Typical Application Schematic" on page 17 for the typical application circuit. 2. All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions. ...
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... Si3050 + Si3011/18/19 Table 2. Loop Characteristics = = (V 3 °C, see Figure 1 on page Parameter Symbol DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage DC Termination Voltage On-Hook Leakage Current Operating Loop Current Operating Loop Current DC Ring Current * Ring Detect Voltage ...
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... Total Supply Current, Deep Sleep Notes not apply to C1A/C2A All inputs at 0 – 0.4 (CMOS levels). All inputs are held static except clock and all outputs unloaded D = (Static I 0 mA). OUT 3. RGDT is not functional in this state. Si3050 + Si3011/18/19 = 3.0 to 3.6 V Symbol Test Condition – ...
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... Si3050 + Si3011/18/19 Table 4. AC Characteristics = = Fs = 8000 Hz, (V 3 ° Parameter Sample Rate PCLK Input Frequency Receive Frequency Response Receive Frequency Response 1 Transmit Full-Scale Level 1,3 Receive Full-Scale Level 4,5,6 Dynamic Range 4,5,6 Dynamic Range 4,5,6 Dynamic Range Transmit Total Harmonic ...
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... ACIM in Register 30. ACIM Table 5. Absolute Maximum Ratings Parameter DC Supply Voltage Input Current, Si3050 Digital Input Pins Digital Input Voltage Ambient Operating Temperature Range Storage Temperature Range Note: Permanent device damage can occur if the above Absolute Maximum Ratings are exceeded. Functional operation should be restricted to the conditions as specified in the operational sections of this data sheet ...
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... Si3050 + Si3011/18/19 Table 6. Switching Characteristics—General Inputs = = = (V 3 ° Parameter Cycle Time, PCLK PCLK Duty Cycle PCLK Jitter Tolerance Rise Time, PCLK Fall Time, PCLK 2 PCLK Before RESET 3 RESET Pulse Width CS, SCLK Before RESET Rise Time, Reset Notes: 1 ...
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... All timing (except Rise and Fall time) is referenced to the 50% level of the waveform. Input test levels are = – 0 0.4 V. Rise and Fall times are referenced to the 20% and 80% levels of the waveform SCLK t su1 CS SDI t d1 SDO Si3050 + Si3011/18/19 20 pF) Test Symbol Conditions su1 ...
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... Si3050 + Si3011/18/19 Table 8. Switching Characteristics—PCM Highway Serial Interface = = = (V 3 ° Parameter Cycle Time PCLK Valid PCLK Inputs 2 FSYNC Period PCLK Duty Cycle PCLK Jitter-Tolerance FSYNC Jitter Tolerance Rise Time, PCLK Fall Time, PCLK Delay Time, PCLK Rise to DTX Active ...
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... FSYNC must be 8 kHz under all operating conditions. 3. Specification applies to PCLK fall to DTX tri-state when that mode is selected. PCLK t su1 FSYNC DRX t d1 DTX Figure 5. GCI Highway Interface Timing Diagram (1x PCLK Mode) Si3050 + Si3011/18/19 20 pF) Test Symbol Conditions ...
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... Si3050 + Si3011/18/19 PCLK FSYNC DRX DTX Figure 6. GCI Highway Interface Timing Diagram (2x PCLK Mode) Table 10. Digital FIR Filter Characteristics—Transmit and Receive = = (V 3.0 to 3.6 V, Sample Rate 8 kHz Parameter Passband (0.1 dB) Passband (3 dB) Passband Ripple Peak-to-Peak Stopband Stopband Attenuation Group Delay Note: Typical FIR filter characteristics for Fs Table 11. Digital IIR Filter Characteristics— ...
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... Figure 8. FIR Receive Filter Passband Ripple For Figures 7–10, all filter plots apply to a sample rate kHz. For Figures 11–14, all filter plots apply to a sample rate kHz. Si3050 + Si3011/18/19 Figure 9. FIR Transmit Filter Response Figure 10. FIR Transmit Filter Passband Ripple Rev. 1.4 15 ...
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... Si3050 + Si3011/18/19 Figure 11. IIR Receive Filter Response Figure 12. IIR Receive Filter Passband Ripple Figure 13. IIR Transmit Filter Response 16 Figure 14. IIR Transmit Filter Passband Ripple Figure 15. IIR Receive Group Delay Figure 16. IIR Transmit Group Delay Rev. 1.4 ...
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... Typical Application Schematic Si3050 + Si3011/18/19 Rev. 1.4 17 ...
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... Si3050 + Si3011/18/19 IGND EPAD EPAD EPAD 47K NI R53 47K NI R52 18 Rev. 1.4 ...
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... R7–R8 may be substituted for R30–R33 and C30–C31 for lower cost, but reduced CID performance. 2. Several diode bridge configurations are acceptable. Parts, such as a single HD04, a DF-04S, or four 1N4004 diodes, may be used (suppliers include General Semiconductor, Diodes Inc., etc.). Si3050 + Si3011/18/19 Value 33 pF, Y2, X7R, ±20% 3.9 nF, 250 V, X7R, ± ...
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... AOUT PWM Output Figure 19 illustrates an optional circuit to support the pulse width modulation (PWM) output capability of the Si3050 for call progress monitoring purposes.To enable this mode, the INTE bit (Register 2) should be set to 0, the PWME bit (Register 1) set to 1, and the PWMM bits (Register 2) set to 00 ...
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... The Si3050 DAA is fully software programmable to meet global requirements and is compliant with FCC, TBR21, JATE, and other country-specific PTT specifications as shown in Table 13. In addition, the Si3050 meets the most stringent global requirements for out-of-band energy, emissions, immunity, high-voltage surges, and safety, including FCC Parts 15 and 68, EN55022, EN55024, and many other standards ...
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... Si3050 + Si3011/18/19 Table 13. Country-specific Register Settings Register 16 Country OHS Argentina 0 1 Australia 1 Austria 0 Bahrain 0 Belgium 0 Brazil 0 Bulgaria 0 Canada 0 Chile 0 China 0 Colombia 0 Croatia 0 Cyprus 0 Czech Republic 0 Denmark 0 Ecuador 0 Egypt 0 El Salvador 0 Finland 0 France 0 Germany 0 Greece 0 Guam 0 Hong Kong 0 Hungary 0 Iceland 0 India 0 Indonesia ...
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... See "5.16. DC Termination" on page 31 for DCV and MINI settings. 2. Supported for loop current 20 mA. 3. TBR21 includes the following countries: Austria, Belgium, Denmark, Finland, France, Germany, Greece, Iceland, Ireland, Italy, Luxembourg, Netherlands, Norway, Portugal, Spain, Sweden, Switzerland, and the United Kingdom. Si3050 + Si3011/18/ ...
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... Si3050 + Si3011/18/19 Table 13. Country-specific Register Settings (Continued) Register 16 Country OHS Slovakia 0 Slovenia 0 South Africa 0 South Korea 0 Spain 0 Sweden 0 Switzerland 0 Taiwan 0 3 TBR21 0 Thailand 0 UAE 0 United Kingdom 0 USA 0 Yemen 0 Note: 1. See "5.16. DC Termination" on page 31 for DCV and MINI settings. 2. Supported for loop current 20 mA. ...
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... Ensure the PDL bit (Register 6, bit 4) is cleared. 2. Set the PDN bit (Register 6, bit 3). 3. The device is now in sleep mode. PCLK must remain active exit sleep mode, reset the Si3050 by pulsing the RESET pin. 5. Program registers to desired settings. signal processing ...
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... The MCAL bit (manual calibration) must be toggled to one and then 0 to begin and complete the calibration. 3. The calibration is completed in 256 ms. 5.7. In-Circuit Testing The Si3050’s advanced design provides the designer with an increased ability to functionality during production line tests and support for end-user diagnostics ...
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... Transmit/Receive Full-Scale Level The Si3050 supports programmable maximum transmit and receive levels. The default signal level supported by the Si3050 is 0 dBm into a 600 load. Two additional modes of operation offer increased transmit and receive level capability to enable use of the DAA in applications that require higher signal levels ...
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... Si3050 + Si3011/18/19 5.12.1. Line Voltage Measurement (Si3011 and Si3019 Line Side Devices Only) The Si3050 reports line voltage with the LVS[7:0] bits (Register 29) in both on- and off-hook states with a resolution per bit. The accuracy of these bits is approximately ±10%. Bits 0 through 7 of this 8-bit signed number indicate the value of the line voltage in 2s complement format ...
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... Loop Current Measurement When the Si3050 is off-hook, the LCS[4:0] bits measure loop current in 3.3 mA/bit resolution. With the LCS[4:0] bits, a user can detect another phone going off-hook by monitoring the dc loop current. The line current sense transfer function is shown in Figure 21 and is detailed in Table 14 ...
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... RGb 4 5 Opto-Relay Figure 22. Typical Application Circuit for Ground Start Support on the SI3050 Table 15. Component Values for the Ground Start Support Schematic Symbol Value 200 ±5% R101 R102, R103, 1 k, 1/10 W, ±5% R106 R104 1.5 k, 1/10 W, ±5% Venkel, SMEC, R105 10 k ...
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... ACIM[3:0] bits in Register 30 are used to select the ac impedance setting. The two available settings for the Si3050 + Si3011 chipset are listed in Table 16. The four available settings for the Si3018 are listed in Table 17 ACIM[3:0] setting other than the four listed in Table 16 or Table 17 is selected, the ac termination is forced to 600 ...
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... Global complex impedance The Si3019 provides sixteen impedances when used with the Si3050. The ACIM[3:0] bits in Register 30 are used to select the ac impedance setting on the Si3019. The sixteen available settings for the Si3019 are listed in Table 18. The most widely used ac terminations are available as ...
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... Ring Detection The ring signal is resistively coupled from TIP and RING to the RNG1 and RNG2 pins. The Si3050 supports either full- or half-wave ring detection. With full-wave ring detection, the designer can detect a polarity reversal of the ring signal. See “5.25.Caller ID” on page 36 ...
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... In a traditional, solid-state dc holding circuit, there are a number of issues in meeting these requirements. The Si3050 dc holding circuit has active control of the on- and off-hook transients to maintain pulse dialing fidelity. Spark quenching requirements in countries, such as Italy, the Netherlands, South Africa, and Australia, deal Rev ...
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... Transient events less than 1 filtered out by the low-pass digital filter on the Si3050 + Si3011 and Si3050+Si3019. The ROV and ROVI bits are set when the received signal is greater than 1.1 V ...
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... Caller ID data can be gained up or attenuated using the receive gain control bits in Registers 39 and 41. 5.25. Caller ID The Si3050 can pass caller ID data from the phone line to a caller ID decoder connected to the DAA. 5.25.1. Type I Caller ID Type I Caller ID sends the CID data when the phone is on-hook ...
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... After allowing the off-hook counter to expire (8 ms), normal transmission and reception can continue. If CID data reception is required, send the appropriate signal to the CO at this time. Figure 26. Implementing Type II Caller ID on the Si3050+Si3011/19 5.26. Overload Detection The Si3050 can be programmed to detect an overload condition that exceeds the normal operating power range of the DAA circuit ...
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... ACIM. The Si3050 also offers a digital hybrid stage for additional near-end echo cancellation. For each ac termination setting, the eight programmable hybrid registers (Registers 45–52) can be programmed with coefficients to increase cancellation of real-world line impedances ...
Page 39
... Filter Selection The Si3050 supports additional filter selections for the receive and transmit signals as defined in Tables 10 and 11. The IIRE bit (Register 16, bit 4) selects between the IIR and FIR filters. The IIR filter provides a shorter, but non-linear, group delay alternative to the default FIR filter, and only operates with an 8 kHz sample rate. The FILT bit (Register 31, bit 1) selects a – ...
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... TXS and RXS registers. These 10-bit values are programmed with the number of PCLK cycles following the rising edge of FSYNC until the data transfer begins. Because the Si3050 looks for the rising edge of FSYNC, both long and short FSYNC pulse widths can be accommodated. A value the PCM Transmit and Receive Start Count registers signifies that the MSB of the data should occur in the same cycle as the rising edge of FSYNC ...
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... By setting the correct starting point of the data, the Si3050 can operate with buses having multiple devices requiring different time slots. The DTX pin is high impedance except during transmission of an 8-bit PCM sample. DTX returns to high impedance either on the negative edge of PCLK during the LSB or on the positive edge of PCLK following the LSB ...
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... Si3050 + Si3011/18/ I Figure 31. PCM Highway Transmission, Long FSYNC (TXS = RXS = 0, PHCF = 0, TRI = 1) PCLK FSYNC PCLK_CNT DRX DTX HI-Z Figure 32. PCM Highway Transmission, Long FSYNC, Delayed Data Transfer MSB MSB (TXS = RXS = 10, PHCF = 0, TRI = 1) Rev LSB LSB HI-Z ...
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... PCLK FSYNC PCLK_CNT DRX M SB DTX HI Figure 33. PCM Highway Double Clocked Transmission, Short FSYNC (TXS = RXS = 0, PHCF = 1, TRI = 1) Si3050 + Si3011/18/ LSB LSB Rev. 1 HI-Z 43 ...
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... Figure 34. 5.34. 16 kHz Sampling Operation in PCM Mode The Si3050 can be configured to support a 16 kHz sampling rate and transmit the data kHz PCM or GCI highway bus. By setting the HSSM bit (Register 7, bit the DAA changes its sampling rate, Fs kHz if it was originally configured for an 8 kHz sampling rate. If µ ...
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... Interval Size Number 256 128 __________________ Notes: 1. Characteristics are symmetrical about analog 0 with sign bit 2. Digital code includes inversion of both sign and magnitude bits. Si3050 + Si3011/18/19 Value at Segment Endpoints Digital Code 8159 10000000b . . . 4319 4063 10001111b . . . 2143 2015 10011111b . . . 1055 991 10101111b ...
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... Si3050 + Si3011/18/19 Table 23. A-Law Encode-Decode Characteristics Segment #Intervals x interval size Number 128 Notes: 1. Characteristics are symmetrical about analog 0 with sign bit 2. Digital code includes inversion of all even numbered bits. 46 Value at segment endpoints Digital Code 4096 3968 10101010b . . 2143 2015 10100101b . . . ...
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... The interface consists of four pins: clock (SCLK), chip select (CS), serial data input (SDI), and serial data output (SDO). In addition, the Si3050 includes a serial data through output pin (SDITHRU) to support daisy chain operation devices. The device can operate with 8-bit and 16-bit SPI controllers. Each SPI operation consists of a control byte, an address byte (of which only the six LSBs are used internally), and either one or two data bytes depending on the width of the controller ...
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... Si3050 + Si3011/18/19 SDO SCLK CPU CS SDI Figure 36. SPI Daisy Chain Control Architecture BRCT R SDI0 SDI1 SDI2 SDI3 SDI14 SDI15 Figure 37. Sample SPI Control Byte to Access Channel 0 48 SCLK SDI CS Channel 0 SDO SDITHRU SDI SCLK CS Channel 1 SDO SDITHRU SCLK SDI CS Channel 15 SDO ...
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... SCLK after the DATA byte to indicate to the state machine that only one byte should be transferred. The state of the SDI pin is ignored during the DATA byte of a read operation CLK S DI CONTROL S DO Figure 41. Write Operation via a 16-bit SPI Port Si3050 + Si3011/18/ DDRE S S ADDRESS A DDRE S S Data [7:0] Rev ...
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... When GCI mode is selected, the sub-frame selection pins must be tied to the correct state to select one of eight sub-frame timeslots in the GCI frame (Table 24). These pins must remain in this state when the Si3050 is operating. Selecting a particular subframe automatically causes that individual Si3050 to transmit and receive on the appropriate sub-frame in the GCI frame, which is initiated by an FSYNC pulse ...
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... MX handshaking bits, located in bits 1 and 0 of the SC channel described below. For purposes of this specification, “downstream” is identified to be the data sent by a host to the Si3050. “Upstream” is identified to be the data sent by the Si3050 to a host. Figure 43 illustrates the Monitor channel communication protocol ...
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... Si3050 always transmits a $FF value on its Monitor data byte. While the Si3050 is transmitting data, the host should always transmit a $FF value on its Monitor byte. If the Si3050 is transmitting data and detects a value other than a $FF on the downstream Monitor byte, the Si3050 signals an Abort. ...
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... A collision occurs on the Monitor data bytes while the Si3050 is transmitting data When the Si3050 aborts because of an invalid command sequence, the state of the Si3050 does not change read or write to an invalid memory address is attempted, all previous reads or writes in that transmission sequence are valid up to the read or write to the invalid memory address ...
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... If the transmitter attempts to signal transmission of a subsequent data byte by placing the downstream MX bit in an inactive state while the Si3050 is still waiting to receive a valid data byte transmission of two consecutive identical data bytes, the Si3050 signals an abort and ends the transmission ...
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... MX: MX bit calculated and expected on DTX line. MXR: MX bit s am pled on DTX line. CLS: Collis ion within the m onitor data byte on DTX line. RQT: Reques t for trans ion from internal s ource. ABT: Abort reques t/indication. Figure 46. Si3050 Monitor Transmitter State Diagram Si3050 + Si3011/18/19 MXR Abort MR x MXR ...
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... Si3050 + Si3011/18/19 56 Rev. 1.4 ...
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... Si3050 + Si3011/18/19 Rev. 1.4 57 ...
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... Upon sending the 2-byte identification code, the Si3050 sends an EOM ( for two consecutive frames. When must the Si3050 signals an abort due to an invalid command. In this mode, bit C is the only other programmable bit Response to CID command from the device using channel B1 is placed in Monitor Data. ...
Page 59
... write is performed to the Si3050’s register read is performed on the Si3050’s register. The CMD[6:0] bits specify the actual command to be performed. CMD[6:0] = 0000001: Read or write a register on the Si3050. CMD[6:0] = 0000010 – 1111111: Reserved. 5.43. Register Address Byte The Register Address byte has the following structure: ADDRESS[7:0] This byte contains the actual 8-bit address of the register to be read or written ...
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... Data that is received must be consistent and match for at least two consecutive frames to be considered valid. When a new command or status is communicated via the C/I bits, the data must be sent for at least two consecutive frames to be recognized by the Si3050. The following steps describe the protocol of how C/I bits are stored, detected, and validated. This is illustrated in Figure 49. ...
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... These bits are defined as follows: CIT6: Reserved CIT5: CVI CIT4: DOD CIT3: INT (represents the state of the INT pin) CIT2: Battery Reversal (represents the state of bit 7 of the LVS register) CIT1: TGD Si3050 + Si3011/18/ CIT3 CIT2 CIT1 C/I Bits Rev. 1.4 ...
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... Si3050 + Si3011/18/19 6. Control Registers Note: Registers not listed here are reserved and must not be written. Register Name 1 Control 1 2 Control 2 3 Interrupt Mask 4 Interrupt Source 5 DAA Control 1 6 DAA Control 2 7 Sample Rate Control 8 Reserved 9 Reserved 10 DAA Control 3 11 System- and Line-Side Device Revision ...
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... Digital loopback across the isolation barrier is disabled Enables digital loopback mode across the isolation barrier. The line-side device must be enabled and off-hook prior to setting this mode. The data path includes the TX and RX filters. 0 Reserved Read returns zero. Si3050 + Si3011/18/ PWMM[1:0] PWME ...
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... Si3050 + Si3011/18/19 Register 2. Control 2 Bit D7 D6 INTE INTP Name R/W R/W Type Reset settings = 0000_0011 Bit Name 7 INTE Interrupt Pin Enable The AOUT/INT pin functions as an analog output for call progress monitoring purposes The AOUT/INT pin functions as a hardware interrupt pin. ...
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... This interrupt is generated from bit 7 of the LVS register. When this bit transitions, it indicates that the polarity of TIP and RING is switched polarity change on TIP and RING does not cause an interrupt on the AOUT/INT pin polarity change on TIP and RING causes an interrupt on the AOUT/INT pin. Si3050 + Si3011/18/ ...
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... Si3050 + Si3011/18/19 Register 4. Interrupt Source Bit D7 D6 RDTI ROVI Name R/W R/W Type Reset settings = 0000_0000 Bit Name 7 RDTI Ring Detect Interrupt ring signal is not occurring ring signal is detected. If the RDTM bit (Register 3) and INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. This bit must be written cleared. ...
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... Bit 7 of the LVS register has transitioned from from indicating the polarity of TIP and RING is switched. If the POLM bit (Register 3) and INTE bit (Register 2) are set, a hardware interrupt occurs on the AOUT/INT pin. To clear the interrupt, write this bit to 0. Si3050 + Si3011/18/19 Function Rev. 1.4 ...
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... Si3050 + Si3011/18/19 Register 5. DAA Control 1 Bit D7 D6 RDTN Name R Type Reset settings = 0000_0000 Bit Name 7 Reserved Read returns zero. 6 RDTN Ring Detect Signal Negative negative ring signal is occurring negative ring signal is occurring. 5 RDTP Ring Detect Signal Positive positive ring signal is occurring. ...
Page 69
... Sample Rate is 8 kHz Sample Rate is 16 kHz. The PCM or the GCI highway continues kHz; thus, twice as many samples are generated per device timeslot. Samples are transmitted in adja- cent timeslots. 2:0 Reserved Read returns zero. Si3050 + Si3011/18/ PDL PDN R/W R/W ...
Page 70
... Si3050 + Si3011/18/19 Register 8-9. Reserved Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 Reserved Read returns zero. Register 10. DAA Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:1 Reserved Read returns zero. 0 DDL Digital Data Loopback Normal operation. ...
Page 71
... These four bits will always read one of the following values, depending on which line-side device is used: Device Si3011 Si3018 Si3019 3:0 REVA[3:0] System-Side Revision. Four-bit value indicating the revision of the Si3050 (system-side) device. Register 12. Line-Side Device Status Bit D7 D6 FDT Name R Type ...
Page 72
... Si3050 + Si3011/18/19 Register 13. Line-Side Device Revision Bit Name R Type Reset settings = xxxx_xxxx Bit Name 7 Reserved Read returns zero. 6 Reserved This bit always reads a one. 5:2 REVB[3:0] Line-Side Device Revision. Four-bit value indicating the revision of the line-side device. 1:0 Reserved Read returns zero. ...
Page 73
... Reset settings = 0000_0000 Bit Name 7 TXM Transmit Mute Transmit signal is not muted Mutes the transmit signal. 6:4 Reserved Read returns zero. 3 RXM Receive Mute Receive signal is not muted Mutes the receive signal. 2:0 Reserved Read returns zero. Si3050 + Si3011/18/ RXM R/W Function Rev. 1 ...
Page 74
... Si3050 + Si3011/18/19 Register 16. International Control 1 Bit D7 D6 OHS Name R/W Type Reset settings = 0000_0000 Bit Name 7 Reserved These bits may be written to a zero or one. 6 OHS On-Hook Speed. Si3018 and Si3019 line-side only. This bit, in combination with the OHS2 bit (Register 31) and the SQ[1:0] bits (Register 59), sets the amount of time for the line-side device to go on-hook ...
Page 75
... BTD bit (Register 17, bit 0) is set to indicate the event. Writing this bit to zero clears the BTD bit Billing tone detection disabled. The BTD bit is not functional Billing tone detection enabled. The BTD bit is not functional. Si3050 + Si3011/18/ ...
Page 76
... Si3050 + Si3011/18/19 Bit Name 1 ROV Receive Overload. This bit is set when the receive input has an excessive input level (i.e., receive pin goes below ground). Writing this location clears this bit and the ROVI bit (Register 4, bit 6 Normal receive input level Excessive receive input level. ...
Page 77
... This bit is used to indicate that the DAA has detected a loop current overload. The detector fir- ing threshold depends on the setting of the ILIM bit (Register 26). OPD ILIM Si3050 + Si3011/18/ Function Overcurrent Threshold Overcurrent Status 160 mA No overcurrent condition exists overcurrent condition exists 160 mA ...
Page 78
... Si3050 + Si3011/18/19 Register 20. Call Progress RX Attenuation Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 ARM[7:0] AOUT Receive Path Attenuation. When decremented from the default setting, these bits linearly attenuate the AOUT receive path signal used for call progress monitoring. Setting the bits to all 0s mutes the AOUT receive path ...
Page 79
... At 20 Hz, TIP/RING events would occur every Hz ms. To calculate the correct RMX[5:0] value for a frequency range [f_min, f_max], the following equation should be used: To compensate for error margin and ensure a sufficient ring detection window recom- mended that the calculated value of RMX[5:0] be incremented by 1. Si3050 + Si3011/18/ RMX[5:0] ...
Page 80
... Si3050 + Si3011/18/19 Register 23. Ring Validation Control 2 Bit D7 D6 RDLY[2] Name R/W Type Reset settings = 0010_1101 Bit Name 7 RDLY[2] Ring Delay Bit 2. This bit, in combination with the RDLY[1:0] bits (Register 22), sets the amount of time between when a ring signal is validated and when a valid ring signal is indicated. ...
Page 81
... RCALD Resistor Calibration Disable Internal resistor calibration enabled Internal resistor calibration disabled. 4 Reserved This bit can be written 3:0 RCAL[3:0] Always write back the value read. Result of resistor calibration. Do not modify this value. Si3050 + Si3011/18/ RAS[5:0] R/W Function 1 ...
Page 82
... Si3050 + Si3011/18/19 Register 26. DC Termination Control Bit D7 D6 DCV[1:0] Name R/W Type Reset settings = 0000_0000 Bit Name TIP/RING Voltage Adjust. Si3018 and Si3019 line-side only. 7:6 DCV[1:0] These bits adjust the voltage on the DCT pin of the line-side device, which affects the TIP/ RING voltage on the line ...
Page 83
... Eight-bit value returning the loop voltage. Each bit represents loop voltage. This regis- ter operates in on- and off-hook modes. Bit seven of this register indicates the polarity of the TIP/RING voltage. When this bit changes state, it indicates that a polarity reversal has occurred. The value returned is represented in 2s complement format. 0000_0000 = No line is connected. Si3050 + Si3011/18/ Function ...
Page 84
... Si3050 + Si3011/18/19 Register 30. AC Termination Control Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:6 Reserved Read returns zero. 5 Reserved This bit may be written to a zero or one. Enhanced Full Scale (2x) Transmit and Receive Mode. 4 FULL2 0 = Default 1 = Transmit/Receive 2x Full Scale This bit changes the full scale of the ADC and DAC from 0 min to +6 dBm into 600 load (or 1 ...
Page 85
... Line Voltage Force Disable (Si3011 and Si3019 line-side only Normal operation The circuitry that forces the LVS register (Register 29) to all less is disabled. The LVS register may display unpredictable values at voltages between All 0s are displayed if the line voltage Si3050 + Si3011/18/ OHS2 ...
Page 86
... Si3050 + Si3011/18/19 Register 32. Ground Start Control Bit D7 D6 Name Type Reset settings = 0000_0x11 Bit Name 7:3 Reserved Read returns zero. 2 TGD TIP Ground Detect The CO has grounded TIP, causing current to flow. When current ceases to flow, this bit returns to a one The CO has not grounded TIP causing current to flow. ...
Page 87
... Always write this bit to zero. 1 PHCF PCM Highway Clock Format PCLK per data bit PCLKs per data bit. 0 TRI Tri-state Bit Tri-state bit 0 on positive edge of PCLK Tri-state bit 0 on negative edge of PCLK. Si3050 + Si3011/18/ PCME PCMF[1:0] R/W R/W Function Rev. 1.4 D2 ...
Page 88
... Si3050 + Si3011/18/19 Register 34. PCM Transmit Start Count—Low Byte Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 TXS[7:0] PCM Transmit Start Count. PCM Transmit Start Count equals the number of PCLKs following FSYNC before data transmission begins. Register 35. PCM Transmit Start Count—High Byte ...
Page 89
... Incrementing the TXG2[3:0] bits results in attenuating the transmit path. 3:0 TXG2[3:0] Transmit Gain 2. Each bit increment represents gain or attenuation maximum of +12 dB and –15 dB respectively. For example: TGA2 TXG2[3: Si3050 + Si3011/18/ Function TGA2 R/W Function Result 0000 0 dB gain or attenuation is applied to the transmit path. 0001 1 dB gain is applied to the transmit path ...
Page 90
... Si3050 + Si3011/18/19 Register 39. RX Gain Control 2 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA2 Receive Gain or Attenuation Incrementing the RXG2[3:0] bits results in gaining up the receive path Incrementing the RXG2[3:0] bits results in attenuating the receive path. ...
Page 91
... Incrementing the TGA3[3:0] bits results in attenuating the transmit path. 3:0 TXG3[3:0] Transmit Gain 3. Each bit increment represents 0 gain or attenuation maximum of 1.5 dB. For example: TGA3 Si3050 + Si3011/18/ TGA3 R/W Function TXG3[3:0] Result 0000 0 dB gain or attenuation is applied to the transmit path. 0001 0.1 dB gain is applied to the transmit path. ...
Page 92
... Si3050 + Si3011/18/19 Register 41. RX Gain Control 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:5 Reserved Read returns zero. 4 RGA3 Receive Gain or Attenuation Incrementing the RXG3[3:0] bits results in gaining up the receive path Incrementing the RXG3[3:0] bits results in attenuating the receive path. ...
Page 93
... B1 channel. 0 B1D Channel B1 Enable Channel B1 transfers are disabled Channel B1 transfers are enabled. If 16-bit linear data format is chosen, disabling the B1 channel results in only the bottom 8 bits of line data being sent and received in the B2 chan- nel. Si3050 + Si3011/18/ GCIF[1:0] R/W Function Rev. 1.4 ...
Page 94
... Si3050 + Si3011/18/19 Register 43. Line Current/Voltage Threshold Interrupt (Si3011 and Si3019 line-side only) Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 CVT[7:0] Current/Voltage Threshold. These bits determine the threshold at which an interrupt is generated from either the LCS or LVS register. This interrupt can be generated to occur when the line current or line voltage rises above or drops below the value in the CVT[7:0] register ...
Page 95
... This register represents the second tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting coefficients for the programmable hybrid. Si3050 + Si3011/18/ ...
Page 96
... Si3050 + Si3011/18/19 Register 47. Programmable Hybrid Register 3 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB3[7:0] Programmable Hybrid Register 3. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the third tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled " ...
Page 97
... This register represents the sixth tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled "5.28. Transhybrid Balance" on page 38 for more information on selecting coefficients for the programmable hybrid. Si3050 + Si3011/18/ ...
Page 98
... Si3050 + Si3011/18/19 Register 51. Programmable Hybrid Register 7 Bit D7 D6 Name Type Reset settings = 0000_0000 Bit Name 7:0 HYB7[7:0] Programmable Hybrid Register 7. These bits can be programmed with a coefficient value to adjust the hybrid response to reduce near-end echo. This register represents the seventh tap in the eight-tap filter. When this register is set to all 0s, this filter stage does not have an effect on the hybrid response. See the section entitled " ...
Page 99
... GCE Guarded Clear Enable (Line-side Revision E or later). This bit (in conjunction with the R2 bit set to 1) enables the Si3050 to meet BT’s Guarded Clear Spec (B5 6450, Part 1: 1993, Section 15.4.3.3). With these bits set, the DAA will draw approximately 2 current from the line while on-hook. ...
Page 100
... AOUT/INT 100 CS GND 1 18 VDD Si3050 Top View DTX C1A 4 15 C2A 5 14 GND RESET 6 13 Figure 50. Si3050 QFN SDITHRU SDO 1 20 SDI 2 19 SCLK GND FSYNC PCLK DTX C1A 15 DRX 7 C2A 14 RGDT 8 RESET TGDE TGD Figure 51. Si3050 TSSOP Rev. 1.4 ...
Page 101
... Control signal for the ground detect relay. Used to support ground start appli- cations RESET Reset Input. An active low input that is used to reset all control registers to a defined, initialized state. Also used to bring the Si3050 out of sleep mode. Si3050 + Si3011/18/19 Description Rev. 1.4 101 ...
Page 102
... A Regulator Voltage Reference. This pin connects to an external capacitor and serves as the reference for the internal voltage regulator Digital Supply Voltage. Provides the 3.3 V digital supply voltage to the Si3050 GND Ground. Connects to the system digital ground SCLK Serial Port Bit Clock Input. ...
Page 103
... Pin Descriptions: Si3011/18/19 Figure 53. Si3011/18/19 SOIC/TSSOP Si3050 + Si3011/18/ DCT3 IGND PAD C1B 4 13 QE2 C2B Figure 52. Si3011/18/19 QFN 1 16 DCT2 DCT IGND DCT3 C1B QE2 6 11 C2B SC VREG 7 10 VREG2 8 RNG1 9 RNG2 Rev. 1.4 103 ...
Page 104
... Si3050 + Si3011/18/19 SOIC/ QFN TSSOP Pin Name Pin # Pin # connect Transistor Emitter. Connects to the emitter of Q3 DCT DC Termination. Provides dc termination to the telephone network Receive Input. Serves as the receive side input from the telephone network Internal Bias. Provides a bias voltage to the device. ...
Page 105
... Table 27. Si3011/18/19 Pin Descriptions (Continued) SOIC/ QFN TSSOP Pin Name Pin # Pin # 17 15 IGND Isolated Ground. Connects to ground on the line-side interface DCT2 DC Termination 2. Provides dc termination to the telephone network. Si3050 + Si3011/18/19 Description Rev. 1.4 105 ...
Page 106
... Si3050 + Si3011/18/19 8. Ordering Guide 1 Part Number Si3050-E-FT System-side Voice DAA Si3050-E-GT System-side Voice DAA Si3050-E-FM System-side Voice DAA Si3050-E-GM System-side Voice DAA Si3011-F-FS Line-side Voice DAA-FCC/TBR21 only Si3011-F-GS Line-side Voice DAA-FCC/TBR21 only Si3011-F-FT Line-side Voice DAA-FCC/TBR21 only Si3011-F-GT Line-side Voice DAA-FCC/TBR21 only ...
Page 107
... The product identification number is a finished goods part number or is specified by a finished goods part number, such as a special customer part number. Example: Si3050-E-FSR Product Designator Product Revision Si3050 + Si3011/18/19 Shipping Option Blank = Tubes R = Tape and Reel Package Type S = SOIC T = TSSOP ...
Page 108
... Si3050 + Si3011/18/19 10. Package Outline: 20-Pin TSSOP Figure 54 illustrates the package details for the Si3050. Table 28 lists the values for the dimensions shown in the illustration. Figure 54. 20-Pin Thin Shrink Small Outline Package (TSSOP) 108 Rev. 1.4 ...
Page 109
... All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Si3050 + Si3011/18/19 Min Nom — — ...
Page 110
... Si3050 + Si3011/18/19 10.1. PCB Land Pattern: Si3050 TSSOP Figure 55. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Table 29. 20-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Dimensions Dimension Notes: 1. This Land Pattern Design is based on IPC-7351 specifications for Density Level B (Median Land Protrusion). ...
Page 111
... Package Outline: 24-Pin QFN Figure 56 illustrates the package details for the Si3050. Table 30 lists the values for the dimensions shown in the illustration. Si3050 + Si3011/18/19 Figure 56. 24-Pin QFN Package Rev. 1.4 111 ...
Page 112
... Si3050 + Si3011/18/19 Table 30. 24-Pin QFN Package Dimensions Dimension aaa bbb ccc ddd eee 112 MIN NOM 0.80 — 0.00 — 0.18 — 4.00 BSC 2.05 2.20 0.50 BSC 4.00 BSC 2.35 2.50 0.30 0.40 0.10 0.10 0.08 0.10 0.05 Rev. 1.4 MAX — ...
Page 113
... PCB Land Pattern: Si3050 QFN Figure 57. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Si3050 + Si3011/18/19 Rev. 1.4 113 ...
Page 114
... Si3050 + Si3011/18/19 Table 31. 24-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions Symbol Notes: General 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing is per the ANSI Y14.5M-1994 specification. 3. This Land Pattern Design is based on the IPC-7351 guidelines. Solder mask design 1 ...
Page 115
... Package Outline: 16-Pin SOIC Figure 58 illustrates the package details for the Si3011/18/19. Table 32 lists the values for the dimensions shown in the illustration. Figure 58. 16-Pin Small Outline Integrated Circuit (SOIC) Package Si3050 + Si3011/18/19 Rev. 1.4 115 ...
Page 116
... Si3050 + Si3011/18/19 Table 32. 16-Pin SOIC Package Diagram Dimensions Dimension θ aaa bbb ccc ddd Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MS-012, Variation AC. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components ...
Page 117
... Notes: 1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P600X165-16N for Density Level B (Median Land Protrusion). 2. All feature sizes shown are at Maximum Material Condition (MMC) and a card fabrication tolerance of 0. assumed. Si3050 + Si3011/18/19 Feature (mm) Pad Column Spacing 5.40 Pad Row Pitch 1.27 Pad Width 0 ...
Page 118
... Si3050 + Si3011/18/19 14. Package Outline: 16-Pin TSSOP Figure 60 illustrates the package details for the Si3011/18/19. Table 34 lists the values for the dimensions shown in the illustration. Figure 60. 16-Pin Thin Shrink Small Outline Package (TSSOP) 118 Rev. 1.4 ...
Page 119
... All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 3. This drawing conforms to the JEDEC Solid State Outline MO-153, Variation AB. 4. Recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Si3050 + Si3011/18/19 Nom Max — 1.20 — ...
Page 120
... Si3050 + Si3011/18/19 14.1. PCB Land Pattern: Si3011/18/19 TSSOP Figure 61. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Pattern Table 35. 16-Pin Thin Shrink Small Outline Package (TSSOP) PCB Land Patten Dimensions Dimension Notes: 1. This Land Pattern Design is based on IPC-7351 specifications for Density Level B (Median Land Protrusion). ...
Page 121
... Package Outline: 20-Pin QFN Figure 62 illustrates the package details for the Si3011/18/19. Table 36 lists the values for the dimensions shown in the illustration. Figure 62. 20-Pin Quad Flat No-Lead (QFN) Package Si3050 + Si3011/18/19 Rev. 1.4 121 ...
Page 122
... Si3050 + Si3011/18/19 Table 36. 20-Pin QFN Package Diagram Dimensions Dimension aaa bbb ccc ddd eee Notes: 1. All dimensions shown are in millimeters (mm) unless otherwise noted. 2. Dimensioning and Tolerancing per ANSI Y14.5M-1994. 122 MIN NOM 0.80 0.85 0.00 0.02 0.20 0.25 0.27 0.32 3.00 BSC 1 ...
Page 123
... PCB Land Pattern: Si3011/18/19 QFN Figure 63. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Si3050 + Si3011/18/19 Rev. 1.4 123 ...
Page 124
... Si3050 + Si3011/18/19 Table 37. 20-Pin Quad Flat No-Lead (QFN) PCB Land Pattern Dimensions Dimension 124 MIN MAX 2.71 REF 1.60 1.80 0.50 BSC 2.71 REF 1.60 1.80 2.53 BSC 2.10 — 2.10 — — 0.34 — 0.28 0.61 REF Rev. 1.4 ...
Page 125
... This provides approximately 70% solder paste coverage on the pad, which is optimum to assure correct component stand-off. Card Assembly 1. A No-Clean, Type-3 solder paste is recommended. 2. The recommended card reflow profile is per the JEDEC/IPC J-STD-020C specification for Small Body Components. Si3050 + Si3011/18/19 MIN MAX — 3.31 — 3.31 Rev ...
Page 126
... Si3050 + Si3011/18/ Si3050 S ILICON ABS AN30: Ground Start Implementation with Silicon Laboratories’ DAAs AN67: Layout Guidelines AN72: Ring Detection/Validation with the Si305x DAAs AN84: Digital Hybrid with the Si305x DAAs Si3050PPT-EVB Data Sheet Note: Refer to www.silabs.com for a current list of support documents for this chipset. ...
Page 127
... Revision 1.1 to Revision 1.31 The internal System-Side Revision value (REVA[3:0] in Register 11) has been incremented by one for Si3050 revision E. Revision 1.31 to Revision 1.4 Added Si3011 device specifications Added Si3050, Si3011, Si3018, and Si3019 QFN information Rev. 1.4 127 ...
Page 128
... Si3050 + Si3011/18/ ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Email: SiDAAinfo@silabs.com Internet: www.silabs.com The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...