AD9949KCPZ Analog Devices Inc, AD9949KCPZ Datasheet - Page 2

IC CCD SIGNAL PROCESSOR 40-LFCSP

AD9949KCPZ

Manufacturer Part Number
AD9949KCPZ
Description
IC CCD SIGNAL PROCESSOR 40-LFCSP
Manufacturer
Analog Devices Inc
Type
CCD Signal Processor, 12-Bitr
Datasheet

Specifications of AD9949KCPZ

Input Type
Logic
Output Type
Logic
Interface
3-Wire Serial
Mounting Type
Surface Mount
Package / Case
40-LFCSP
Analog Front End Type
CCD
Analog Front End Category
Video
Interface Type
Serial (3-Wire)
Sample Rate
36MSPS
Input Voltage Range
0.5V
Operating Supply Voltage (min)
2.7V
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.6V
Resolution
12b
Number Of Adc's
1
Power Supply Type
Analog/Digital
Operating Temp Range
-20C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
40
Package Type
LFCSP EP
Number Of Channels
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Lead Free Status / RoHS Status
Compliant, Lead free / RoHS Compliant

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AD9949
TABLE OF CONTENTS
Specifications..................................................................................... 3
Absolute Maximum Ratings............................................................ 6
Pin Configuration and Function Descriptions............................. 7
Terminology ...................................................................................... 8
Equivalent Input/Output Circuits .................................................. 9
Typical Performance Characteristics ........................................... 10
System Overview ............................................................................ 11
Serial Interface Timing .................................................................. 12
Complete Register Listing ............................................................. 13
Precision Timing High Speed Timing Generation...................... 18
Horizontal Clamping and Blanking ............................................. 21
REVISION HISTORY
11/04—Data Sheet Changed from Rev. A to Rev. B
Changes to Ordering Guide .......................................................... 35
9/04—Data Sheet Changed from Rev. 0 to Rev. A
Changes to Features.......................................................................... 1
Changes to Analog Specifications .................................................. 4
Changes to Terminology Section.................................................... 9
Added H-Counter Behavior Section............................................ 12
Changes to Table 7.......................................................................... 14
General Specifications ................................................................. 3
Digital Specifications ................................................................... 3
Analog Specifications................................................................... 4
Timing Specifications .................................................................. 5
Thermal Characteristics .............................................................. 6
ESD Caution.................................................................................. 6
H-Counter Behavior .................................................................. 11
Timing Resolution...................................................................... 18
High Speed Clock Programmability ........................................ 18
H-Driver and RG Outputs ........................................................ 19
Digital Data Outputs.................................................................. 19
Individual CLPOB and PBLK Sequences................................ 21
Rev. B | Page 2 of 36
Generating Special HBLK Patterns .............................................. 23
Power-Up Procedure...................................................................... 25
Analog Front End Description and Operation .......................... 26
Applications Information .............................................................. 30
Outline Dimensions ....................................................................... 34
Changes to Table 12 ....................................................................... 17
Changes to Table 15 ....................................................................... 17
Changes to H-Counter Sync Section ........................................... 24
Changes to Recommended Power-Up Sequence Section ......... 25
Changes to Ordering Guide .......................................................... 35
5/03—Revision 0: Initial Version
Individual HBLK Sequences..................................................... 21
Horizontal Sequence Control ................................................... 23
External HBLK Signal................................................................ 23
H-Counter Synchronization ..................................................... 24
Recommended Power-Up Sequence ....................................... 25
DC Restore .................................................................................. 26
Correlated Double Sampler ...................................................... 26
PxGA............................................................................................ 26
Variable Gain Amplifier ............................................................ 29
ADC ............................................................................................. 29
Optical Black Clamp .................................................................. 29
Digital Data Outputs.................................................................. 29
Circuit Configuration ................................................................ 30
Grounding and Decoupling Recommendations.................... 30
Driving the CLI Input................................................................ 31
Horizontal Timing Sequence Example.................................... 31
Ordering Guide .......................................................................... 34

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