AD9805JS Analog Devices Inc, AD9805JS Datasheet
AD9805JS
Specifications of AD9805JS
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AD9805JS Summary of contents
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FEATURES Pin Compatible 12-Bit and 10-Bit Versions 12-Bit/10-Bit 6 MSPS A/D Converter Integrated Triple Correlated Double Sampler 3-Channel, 2 MSPS Color Mode 1 – 4 Analog Programmable Gain Amplifier Pixel-Rate Digital Gain Adjustment Pixel-Rate Digital Offset Adjustment Internal Voltage ...
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AD9807–SPECIFICATIONS ANALOG SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE 3-Channel Mode With CDS 1 1-Channel Mode With CDS DC ACCURACY 2 Integral Nonlinearity (INL) 2 Differential Nonlinearity (DNL) No Missing Codes Unipolar Offset Error (@ +25 C) Gain Error (@ +25 C) ...
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AD9805–SPECIFICATIONS ANALOG SPECIFICATIONS Parameter RESOLUTION CONVERSION RATE 3-Channel Mode With CDS 1 1-Channel Mode With CDS DC ACCURACY 2 Integral Nonlinearity (INL) 2 Differential Nonlinearity (DNL) No Missing Codes Unipolar Offset Error (@ +25 C) Gain Error (@ +25 C) ...
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AD9807/AD9805 TIMING SPECIFICATIONS (T Parameter CLOCK PARAMETERS 3-Channel Conversion Rate 1-Channel Conversion Rate CDSCK1 Pulse Width CDSCK1 Pulse Width CDSCK2 Pulse Width CDSCK2 Pulse Width CDS Clocks Digital Quiet Time CDSCK2 Falling to CDSCK1 Rising CDSCK2 Falling to CDSCK1 Rising ...
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AVDD AVSS CAPT CAPT CAPB CAPB VREF CML VINR AVSS VING AVSS VINB AVSS AVDD STRTLN Pin No. Pin Name 1, 15 AVDD 2, 10, 12, 14 AVSS 3, 4 CAPT 5, 6 CAPB 7 VREF 8 CML 9 VINR ...
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AD9807/AD9805 CONNECT Pin No. Pin Name 1, 15 AVDD 2, 10, 12, 14 AVSS 3, 4 CAPT 5, 6 CAPB 7 VREF 8 CML 9 VINR 11 VING 13 VINB 16 STRTLN 17 CDSCLK1 18 CDSCLK2 19 ...
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... Package Model Range Description AD9807JS +70 C PQFP AD9805JS +70 C PQFP *S = Plastic Quad Flatpack. CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the AD9807/AD9805 feature proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges ...
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AD9807/AD9805 ANALOG INPUTS t AD STRTLN t C1C2A t C1A CDSCLK1 t C1AD CDSCLK2 t ACLK ADCCLK R GAIN<n:0> OFFSET<m:0> ANALOG INPUTS (0V) STRTLN CDSCLK1 t ACLK ADCCLK GAIN<n:0> OFFSET<m:0> ANALOG t INPUTS AD STRTLN t C1B t ...
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ANALOG t INPUTS AD STRTLN t C1B t C1C2B CDSCLK1 t C1AD CDSCLK2 t ACLK ADCCLK GAIN<n:0> OFFSET<m:0> G0 Figure 1d. 1-Channel CDS-Mode Clock Timing (Red Channel) ANALOG INPUTS (0V) STRTLN CDSCLK1 t ACLK ADCCLK GAIN<n:0> G0 OFFSET<m:0> Figure 1e. ...
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AD9807/AD9805 ANALOG INPUTS STRTLN CDSCLK1 t Q CDSCLK2 t Q ADCCLK R G GAIN<n:0> OFFSET<m:0> OEB CSB A0, A1, A2 WRB MPU<7:0> CSB A0, A1, A2 RDB MPU<7:0> R0, G0, B0 R1, G1 ...
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RED VINR CDS PGA GREEN VING PGA CDS BLUE VINB PGA CDS CDSCLK1 CDSCLK2 STRTLN ADCCLK REGISTER OVERVIEW MPU Port Map Table II shows the MPU Port Map. The MPU Port Map is accessed through pins A0, ...
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AD9807/AD9805 Color Pointer Both the AD9807 and the AD9805 use Bits 6 and 7 in the Configuration Register to direct data to the corresponding internal registers. Table III shows the mapping of Bits 6 and 7 to their corresponding color. ...
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LSBs and negative 128 LSBs. The offset is variable in 1 LSB increments (see Table V). The contents of the color pointer in the Configuration Register at the time an Odd or Even Register is written indicates the color ...
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AD9807/AD9805 3-Channel SHA Operation This mode of the AD9807/AD9805 enables 3-channel simulta- neous sampling; it differs from the CDS sampling mode in that the CDS functions are replaced with sample-and-hold amplifiers (SHAs). CDSCLK1 becomes the sample-and-hold clock; CDSCLK2 is tied ...
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PGA; the setting in the corre- sponding PGA Gain Register determines the gain of the PGA. The output from the PGA is then routed through a high speed multiplexer to a 12-bit A/D converter ...
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AD9807/AD9805 PIXEL n RIN, GIN, BIN CDSCLK1 ADCCLK R DATA<11:0> GAIN<n:0> R (n) G (n) GAIN<m:0> PIXEL n RIN, GIN, BIN CDSCLK1 CDSCLK2 ADCCLK D (n–8) DATA<11:0> GAIN<n:0> G (n) OFFSET<m:0> PIXEL n RIN, GIN, BIN CDSCLK1 ADCCLK DATA<11:0> GAIN<n:0> ...
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Calculating Overall Gain The overall gain for the AD9807/AD9805 can accommodate a wide range of input voltage spans. The total gain is a composite of analog gain (from the PGAs), digital gain (from the digital multiplier) and the input span ...
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AD9807/AD9805 discharging include the amount of time that input switch S1 is turned on, the input impedance of the AD9807/AD9805 and the output impedance of the circuit driving the coupling capacitor. The impedance of the drive circuit, R impedance of ...
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Power-On Initialization and Calibration Sequence When the AD9807/AD9805 is powered on, the following sequence should be used to initialize the part to a known state. The digital gain and offset buses are disabled until the calibra- tion sequence. The Bayer ...
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AD9807/AD9805 SET PGA AND INPUT OFFSET FOR GREEN PIXELS USING THE GREEN REGISTERS SET PGA AND INPUT OFFSET FOR RED PIXELS USING THE BLUE REGISTERS BRING STRTLN LOW WRITE A "1" TO THE LSB OF THE BAYER REGISTER APPLY AT ...
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CIS Application Unlike many other integrated circuit CCD signal processors, the AD9807/AD9805 can easily be implemented in imaging systems that do not use a CCD. By disabling the input clamp and the CDS blocks, any dc coupled signal within the ...
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AD9807/AD9805 AVDD +5VD DVDD + C21 C18 + C26 C25 0.1µF 10µF 0.1µF 10µF AVSS TP13 TP14 TP15 TP16 TP5 C1 + C28 C27 0.01µF 10µF 0.1µ JP1 C2 0.01µ JP2 C3 ...
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C27 C4 C11 Figure 27. Suggested Capacitor Placement for Single-Side Component Layout REV. 0 C15 C14 –23– AD9807/AD9805 ...
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AD9807/AD9805 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 64-Terminal PQFP (S-64) 0.687 (17.45) 0.667 (16.95) 0.555 (14.10) 0.093 (2.35) MAX 0.547 (13.90) 0.472 (12.0) BSC 0.041 (1.03) 0.029 (0.73 PIN 1 SEATING PLANE TOP VIEW ...