AD9821KST Analog Devices Inc, AD9821KST Datasheet - Page 9

• Manufacturer Part Number: AD9821KST
• Description: IC IMAGE SGNL PROC 12BIT 48-LQFP
• Manufacturer: Analog Devices Inc
• Type: Image Sensorr

Specifications of AD9821KST

• Rohs Status: RoHS non-compliant
• Input Type: Logic
• Output Type: Logic
• Interface: 3-Wire Serial
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Analog Front End Type: CCD
• Analog Front End Category: Video
• Interface Type: Serial (3-Wire)
• Sample Rate: 40MSPS
• Input Voltage Range: 0.5V
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Resolution: 12b
• Number Of Adc's: 1
• Power Supply Type: Analog/Digital
• Operating Temp Range: -20C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Package Type: LQFP
• Number Of Channels: 1
• Current - Supply: -
• Lead Free Status / RoHS Status: Not Compliant

INTERNAL REGISTER MAP AND SERIAL INTERFACE TIMING
Register
Name
Operation
VGA Gain
Clamp Level
Control
NOTES
1
2
REV. 0
Internal use only. Must be set to 0.
Must be set to 1.
SDATA
SCK
NOTES:
1. ANY NUMBER OF ADJACENT REGISTERS MAY BE LOADED SEQUENTIALLY, BEGINNING WITH THE LOWEST ADDRESS AND INCREMENTING ONE ADDRESS AT A TIME.
2. WHEN SEQUENTIALLY LOADING MULTIPLE REGISTERS, THE EXACT REGISTER LENGTH (SHOWN ABOVE) MUST BE USED FOR EACH REGISTER.
3. ALL LOADED REGISTERS WILL BE SIMULTANEOUSLY UPDATED WITH THE RISING EDGE OF SL.
SL
SDATA
SDATA
SCK
SCK
SL
SL
RNW
A0 A1 A2
0 0 0
1 0 0
0 1 0
1 1 0
t
NOTES:
1. SDATA BITS ARE INTERNALLY LATCHED ON THE RISING EDGES OF SCK.
2. RNW = READ-NOT WRITE. SET LOW FOR WRITE OPERATION.
3. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
4. SYSTEM UPDATE OF LOADED REGISTERS OCCURS ON SL RISING EDGE.
NOTES:
1. RNW = READ-NOT WRITE. SET HIGH FOR READ OPERATION.
2. TEST BITS = INTERNAL USE ONLY. MUST BE SET LOW.
3. SERIAL DATA FROM THE SELECTED REGISTER IS VALID STARTING AFTER THE FIFTH SCK FALLING EDGE, AND IS UPDATED ON
Address
DS
0
t
1
DS
SCK FALLING EDGES.
A0 A1
0
2
RNW
RNW
0
0
1
3
A2
t
t
0
LS
LS
4
A0
A0
t
Input Mode
Selection
LSB
0
0
D0 D1 D2
LSB
DH
t
DH
1
5
Figure 9. Continuous Serial Write Operation to All Registers
D0
A1
A1
6
D1
0
7
1
OPERATION
A2
0
11 BITS
D2
8
TEST BIT
TEST BIT
D3
Figure 8. Serial Readback Operation
9
D3
Power-Down
Modes
0
0
0
1
Figure 7. Serial Write Operation
...
...
Table I. Internal Register Map
D0
D10 D0
D0
16
t
DV
Data Bits
D4
0
1
17
D1
D1
D1
18
D2
VGA GAIN
D2
Software OB Clamp
Reset
0
D5
D2
–9–
10 BITS
19
1
D3
20
D3
D3
...
...
D6
On/Off
Clock Polarity Select for
CLP/DATA
D4
D9
D4
26
D0
27
D5
D5
D1
28
CLAMP LEVEL
D6
D2
29
D6
8 BITS
D3
30
D7
0
D7
D7
1
...
...
D7
D8
34
D8
D8
1
MSB
0
D0
2
1
35
D9
D9
D1
t
t
36
LH
LH
CONTROL
D2
10 BITS
D10
37
D9
0
X
0
D10
1
1
D3
38
AD9821
...
...
...
D10
0
MSB
X
0
1
1
D9
44
0
X
X
X
1