AD9840AJST Analog Devices Inc, AD9840AJST Datasheet
AD9840AJST
Specifications of AD9840AJST
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AD9840AJST Summary of contents
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PBLK CCDIN CLPDM AUX1IN AUX2IN CLP AD9840A PRODUCT DESCRIPTION The AD9840A is a complete analog signal processor for CCD applications. It features a 40 MHz single-channel architecture designed to sample and condition the outputs of interlaced and progressive scan ...
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AD9840A–SPECIFICATIONS GENERAL SPECIFICATIONS Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE Analog, Digital, Digital Driver POWER CONSUMPTION Normal Operation Power-Down Modes Fast Recovery Mode Standby Total Power-Down MAXIMUM CLOCK RATE A/D CONVERTER Resolution Differential Nonlinearity (DNL) No Missing Codes Full-Scale ...
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CCD-MODE SPECIFICATIONS Parameter P OWER CONSUMPTION MAXIMUM CLOCK RATE CDS 1 Allowable CCD Reset Transient 1 Max CCD Black Pixel Amplitude 1 Max Input Range before Saturation Max Input Range before Saturation Max Input Range before Saturation Max Output Range ...
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AD9840A–SPECIFICATIONS AUX1-MODE SPECIFICATIONS Parameter POWER CONSUMPTION MAXIMUM CLOCK RATE INPUT BUFFER Gain Max Input Range VGA Max Output Range Gain Control Resolution Gain (Selected Using VGA Gain Register) Min Gain Max Gain Specifications subject to change without notice. AUX2-MODE SPECIFICATIONS ...
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... CDM t 2 COB INH 7 SCLK Model Unit AD9840AJST –20°C to +85° THERMAL CHARACTERISTICS V Thermal Resistance V 48-Lead LQFP Package V θ = 92° °C 150 °C 300 AD9840A Typ Max 12 12.5 3.0 14.5 16 7.6 9 ORDERING GUIDE Temperature Package Package Range Description Option Thin Plastic ...
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AD9840A CONNECT Pin Number Name 1, 2 DRVSS 3–12 D0–D9 13 DRVDD 14 DRVSS 15, 18, 24, 41 DVSS 16 DATACLK 17 DVDD1 19 PBLK 20 CLPOB 21 SHP 22 SHD 23 CLPDM 25, 26, 35 AVSS ...
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DEFINITIONS OF SPECIFICATIONS DIFFERENTIAL NONLINEARITY (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 10-bit ...
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AD9840A CCD-MODE AND AUX-MODE TIMING CCD SIGNAL SHP t S1 SHD t INH DATACLK t OD OUTPUT N–10 DATA NOTES: 1. RECOMMENDED PLACEMENT FOR DATACLK RISING EDGE IS BETWEEN THE SHD RISING EDGE AND NEXT ...
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SERIAL INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION Register Address Name Operation Channel Select CCD/AUX VGA Gain LSB Clamp Level LSB Control CDS Gain ...
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AD9840A Table II. Operation Register Contents (Default Value x000) D10 Must be set to zero. Set to one. Table III. VGA Gain Register Contents (Default Value x096) MSB D10 D9 D8 ...
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DC RESTORE 0.1 F CCDIN CLPDM CIRCUIT DESCRIPTION AND OPERATION The AD9840A signal processing chain is shown in Figure 11. Each processing step is essential in achieving a high-quality image from the raw CCD pixel data. DC Restore To reduce ...
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AD9840A together with CLPOB or separately. The CLPDM pulse should be a minimum of four pixels wide. Variable Gain Amplifier The VGA stage provides a gain range dB, program- mable with 10-bit resolution through the ...
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F INPUT SIGNAL 0.4V AUX2IN VIDEO SIGNAL 0.1 F Table VIII. VGA Gain Register Used for AUX2-Mode MSB D10 0.4V 0dB TO 36dB 5k ...
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AD9840A CCD V OUT V-DRIVE APPLICATIONS INFORMATION The AD9840A is a complete Analog Front End (AFE) product for digital still camera and camcorder applications. As shown in Figure 16, the CCD image (pixel) data is buffered and sent to the ...
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SERIAL INTERFACE DRVSS 1 DRVSS PIN 1 2 IDENTIFIER (LSB AD9840A 6 D4 TOP VIEW 7 (Not to Scale ...
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AD9840A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 48-Lead LQFP (ST-48) 0.063 (1.60) MAX 0.354 (9.00) BSC SQ 0.030 (0.75 0.018 (0.45 TOP VIEW (PINS DOWN) COPLANARITY 12 25 0.003 (0.08 MIN ...