CYV15G0204RB-BGXC Cypress Semiconductor Corp, CYV15G0204RB-BGXC Datasheet
CYV15G0204RB-BGXC
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CYV15G0204RB-BGXC Summary of contents
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... BIST) with other HOTLink devices. Each channel of the CYV15G0204RB Dual HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction ...
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... CYV15G0204RB Deserializing Reclocker Logic Block Diagram Reclocker Document #: 38-02103 Rev. *C x10 x10 Deserializer Deserializer RX Reclocker CYV15G0204RB RX Page [+] Feedback ...
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... RXBISTA[1:0] RXRATEA Recovered Serial Data Reclocker ROE[2..1]A Output PLL Clock Multiplier RXBISTB[1:0] RXRATEB Recovered Serial Data Reclocker ROE[2..1]B Output PLL Clock Multiplier B CYV15G0204RB = Internal Signal RESET TRST JTAG TMS Boundary TCLK Scan TDI Controller TDO LFIA 10 RXDA[9:0] BISTSTA ÷2 RXCLKA+ RXCLKA– ...
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... Device Configuration and Control Block Diagram WREN Device Configuration ADDR[2:0] and Control Interface DATA[6:0] Document #: 38-02103 Rev. *C CYV15G0204RB RXBIST[A..B] RXRATE[A..B] SDASEL[A..B][1:0] RXPLLPD[A..B] ROE[2..1][A..B] = Internal Signal Page [+] Feedback ...
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... GND DB[3] [0] CLKB– RX BIST TRG RE GND GND GND DB[1] STB CLKB+ CLKOA RX ADDR ADDR RX RE GND GND DB[0] [2] [1] CLKA+ PDOA GND NC GND GND DB[2] CLKOB CLKA– CYV15G0204RB ROUT A2– A2– IN ROUT A2+ A2+ SPD LDTD TRST TDO NC V GND ...
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... GND GND GND GND GND CLKB– [0] RE TRG BIST GND GND GND GND CLKOA CLKB+ STB RE RX ADDR ADDR GND GND GND PDOA CLKA+ [1] [ GND GND GND NC GND CLKA– CLKOB CYV15G0204RB ROUT B1– B1– ROUT B1+ B1+ ULCB TMS TDI ...
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... Pin Definitions CYV15G0204RB Dual HOTLink II Deserializing Reclocker Name I/O Characteristics Signal Description Receive Path Data and Status Signals RXDA[9:0] LVTTL Output, RXDB[9:0] synchronous to the RXCLK± output BISTSTA LVTTL Output, BISTSTB synchronous to the RXCLKx ± output REPDOA Asynchronous to REPDOB reclocker output ...
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... Pin Definitions (continued) CYV15G0204RB Dual HOTLink II Deserializing Reclocker Name I/O Characteristics Signal Description LDTDEN LVTTL Input, internal pull-up ULCA LVTTL Input, ULCB internal pull-up [2] SPDSELA 3-Level Select SPDSELB static control input INSELA LVTTL Input, INSELB asynchronous LFIA LVTTL Output, LFIB asynchronous ...
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... Pin Definitions (continued) CYV15G0204RB Dual HOTLink II Deserializing Reclocker Name I/O Characteristics Signal Description DATA[6:0] LVTTL input asynchronous, internal pull-up Internal Device Configuration Latches [4] RXRATE[A..B] Internal Latch [4] SDASEL[2..1][A..B] Internal Latch [1:0] [4] RXPLLPD[A..B] Internal Latch [4] RXBIST[A..B][1:0] Internal Latch [4] ROE2[A..B] Internal Latch [4] ROE1[A ...
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... I/O Characteristics Signal Description Power V CC GND CYV15G0204RB HOTLink II Operation The CYV15G0204RB is a highly configurable, independent clocking, dual-channel reclocking deserializer designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations. This device supports two 10-bit channels. ...
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... Receive Channel Enabled The CYV15G0204RB contains two receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface. When the RXPLLPDx latch = 0, the associated PLL and analog circuitry of the channel is disabled ...
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... Device Reset State When the CYV15G0204RB is reset by assertion of RESET, all state machines, counters, and configuration latches in the device are initialized to a reset state. Additionally, the JTAG controller must also be reset for valid operation (even if JTAG testing is not performed). See “ ...
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... If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Document #: 38-02103 Rev. *C CYV15G0204RB Page [+] Feedback ...
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... BIST data reception (RXBISTx[1:0] = 10). [Required step] JTAG Support The CYV15G0204RB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs and the TRGCLKx± ...
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... Monitor Data Received {BISTSTx, RXDx[0], RXDx[1]} = BIST_START (101) Start of BIST Detected Compare Next Character Match End-of-BIST State Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_LAST_GOOD (010) BIST_ERROR (110) CYV15G0204RB Receive BIST Detected LOW RX PLL Out of Lock {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) No Page [+] Feedback ...
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... Document #: 38-02103 Rev. *C Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0204RB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range + 0.5V CC ...
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... CYV15G0204RB DC Electrical Characteristics Parameter Description Differential CML Serial Outputs: ROUTA1±, ROUTA2±, ROUTB1±, ROUTB2± V Output HIGH Voltage OHC (V Referenced Output LOW Voltage OLC (V Referenced Output Differential Voltage ODIF |(OUT+) − (OUT−)| Differential Serial Line Receiver Inputs: INA1±, INA2±, INB1±, INB2± ...
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... TRGCLKx Fall Time (20%–80%) TRGF [21] t TRGCLKx Frequency Referenced to Received Clock Frequency TRGRX CYV15G0204RB Bus Configuration Write Timing Characteristics Over the Operating Range t Bus Configuration Data Hold DATAH t Bus Configuration Data Setup DATAS t Bus Configuration WREN Pulse Width ...
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... CYV15G0204RB AC Electrical Characteristics Parameter CYV15G0204RB Reclocker Serial Output Characteristics Over the Operating Range Parameter Description t Bit Time B [14] t CML Output Rise Time 20−80% (CML Test Load) RISE [14] t CML Output Fall Time 80−20% (CML Test Load) FALL PLL Characteristics Parameter Description ...
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... Switching Waveforms for the CYV15G0204RB HOTLink II Receiver Receive Interface Read Timing RXRATEx = 1 RXCLKx+ RXCLKx– RXDx[9:0] CYV15G0204RB HOTLink II Bus Configuration Switching Waveforms Bus Configuration Write Timing ADDR[2:0] DATA[6:0] WREN Document #: 38-02103 Rev. *C (continued) t RXCLKP t RXDV– t RXDV+ t WRENP t DATAS CYV15G0204RB t DATAH ...
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... VCC POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER E19 VCC POWER E20 VCC POWER F01 NC NO CONNECT CYV15G0204RB Ball Signal Name Signal Type ID F17 VCC POWER F18 NC NO CONNECT F19 NC NO CONNECT F20 NC NO CONNECT G01 GND GROUND ...
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... RXDA[9] LVTTL OUT V18 RXDA[5] LVTTL OUT V19 RXDA[2] LVTTL OUT V20 RXDA[1] LVTTL OUT W01 VCC POWER W02 VCC POWER CYV15G0204RB Ball Signal Name Signal Type ID L20 GND GROUND M01 NC NO CONNECT M02 NC NO CONNECT W03 LFIB LVTTL OUT W04 RXCLKB– ...
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... Ordering Information Speed Ordering Code Standard CYV15G0204RB-BGC Standard CYV15G0204RB-BGXC Package Diagram Figure 3. 256-Lead L2 Ball Grid Array ( 1.57 mm) BL256 TOP VIEW 27.00±0.13 A1 CORNER I.D. 1.57±0.175 0.97 REF. 0.60±0.10 C SIDE VIEW HOTLink is a registered trademark and HOTLink II and MultiFrame are trademarks of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders ...
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... Document History Page Document Title: CYV15G0204RB Independent Clock Dual HOTLink II™ Reclocking Deserializer Document Number: 38-02103 ISSUE REV. ECN NO. DATE ** 246850 See ECN *A 338721 See ECN *B 384307 See ECN *C 1034083 See ECN Document #: 38-02103 Rev. *C ORIG. OF DESCRIPTION OF CHANGE CHANGE FRE New Data Sheet ...