CYV15G0204TRB-BGC Cypress Semiconductor Corp, CYV15G0204TRB-BGC Datasheet

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... CYV15G0204TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. Each transmit (TX) channel of the CYV15G0204TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from ...

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... Each receive (RX) channel of the CYV15G0204TRB HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs ...

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... Clock Multiplier Character-Rate Clock A TXBISTA PABRSTA Bit-Rate Clock B Transmit PLL Transmit PLL OEB[2..1] Clock Multiplier B Clock Multiplier Character-Rate Clock B PABRSTB TXBISTB CYV15G0204TRB = Internal Signal RESET OEA[2..1] OUTA1+ OUTA1– OUTA2+ OUTA2– OEB[2..1] OUTB1+ OUTB1– OUTB2+ OUTB2– Page [+] Feedback ...

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... RXRATEC Recovered Serial Data Reclocker ROE[2..1]C Output PLL Clock Multiplier RXBISTD[1:0] RXRATED Recovered Serial Data Reclocker ROE[2..1]D Output PLL Clock Multiplier D CYV15G0204TRB = Internal Signal RESET TRST JTAG TMS TCLK Scan TDI TDO LFIC 10 RXDC[9:0] BISTSTC ÷2 RXCLKC+ RXCLKC– ...

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... Device Configuration and Control Block Diagram WREN Device Configuration ADDR[3:0] and Control Interface DATA[6:0] Document #: 38-02101 Rev. *B CYV15G0204TRB Internal Signal = TXRATE[A..B] TXCKSEL[A..B] PABRST[A..B] TOE[2..1][A..B] TXBIST[A..B] RXRATE[C..D] SDASEL[2..1][C..D][1:0] TRGRATE[C..D] RXPLLPD[C..D] RXBIST[C..D][1:0] ROE[2..1][C..D] Page [+] Feedback ...

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... CLKD– DA[1] RX BIST ADDR TRG TX GND GND DD[1] STD [2] CLKD+ CLKOA RX ADDR ADDR TX GND NC GND DD[0] [3] [1] ERRA GND NC NC GND DD[2] CLKOD CLKA CYV15G0204TRB TOUT TOUT TOUT GND A2– B1– B2– TOUT TOUT TOUT A2+ B1+ B2+ SPD LDTD TRST TDO ...

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... CLKD– [0] DA[ TRG ADDR BIST GND GND DA[3] CLKOA CLKD+ [2] STD TX TX ADDR ADDR GND NC GND DA[2] ERRA [1] [ GND NC NC GND DA[0] CLKA CLKOD CYV15G0204TRB ROUT IN ROUT IN ROUT D1– D1– C2– C2– C1– C1– ROUT IN ROUT IN ROUT D1+ D1+ C2+ C2+ C1+ C1+ ...

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... Pin Definitions CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description Transmit Path Data and Status Signals TXDA[7:0] LVTTL Input, TXDB[7:0] synchronous, sampled by the associated TXCLKx↑ or [2] REFCLKx↑ TXERRA LVTTL Output, TXERRB synchronous to [3] REFCLKx↑ ...

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... Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description Receive Path Data and Status Signals RXDC[9:0] LVTTL Output, RXDD[9:0] synchronous to the RXCLK± output BISTSTC LVTTL Output, BISTSTD synchronous to the RXCLKx ± output REPDOC ...

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... Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description LDTDEN LVTTL Input, internal pull-up ULCC LVTTL Input, ULCD internal pull-up [4] SPDSELA 3-Level Select SPDSELB static control input SPDSELC SPDSELD INSELC LVTTL Input, INSELD asynchronous ...

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... Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name I/O Characteristics Signal Description DATA[6:0] LVTTL input asynchronous, internal pull-up Internal Device Configuration Latches [6] RXRATE[C..D] Internal Latch [6] SDASEL[2..1][C..D] Internal Latch [1:0] [6] TXCKSEL[A..B] Internal Latch [6] TXRATE[A..B] Internal Latch [6] TRGRATE[C..D] ...

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... TXCLKOx. Each clock multiplier PLL can accept a REFCLKx± input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0204TRB clock multiplier (TXRATEx) and by the level on the associated SPDSELx input. SPDSELx are 3-level select operating ranges for the serial data outputs and inputs of the associated channel ...

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... Signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mV. Document #: 38-02101 Rev. *B CYV15G0204TRB Receive Data Path Serial Line Receivers Signaling Two differential Line Receivers, INx1± and INx2±, are Rate (Mbps) available on each channel for accepting serial data streams ...

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... Receive Channel Enabled The CYV15G0204TRB contains two receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface. When the RXPLLPDx latch = 0, the associated PLL and analog circuitry of the channel is disabled ...

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... Device Reset State When the CYV15G0204TRB is reset by assertion of RESET, all state machines, counters, and configuration latches in the device are initialized to a reset state. See Table 4 for the initialize values of the configuration latches. ...

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... When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV. When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV. Document #: 38-02101 Rev. *B CYV15G0204TRB configured with their corresponding value each time that their associated latch bank is configured. The latches that have an ‘ ...

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... Set the static latch banks for the target channel. Document #: 38-02101 Rev. *B CYV15G0204TRB 3. Set the dynamic bank of latches for the target channel. Enable the Receive PLLs and transmit channels receive channel is enabled, set the channel for SMPTE data reception (RXBISTA[1:0] = 01) or BIST data reception (RXBISTA[1:0] = 10) ...

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... JTAG Support The CYV15G0204TRB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs, the REFCLKx± clock inputs, and the TRGCLKx± clock inputs. The high-speed serial inputs and outputs are not part of the JTAG test chain ...

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... RXDx[1]} = BIST_START (101) Start of BIST Detected Compare Next Character Match End-of-BIST State Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_LAST_GOOD (010) BIST_ERROR (110) Figure 2. Receive BIST State Machine CYV15G0204TRB Receive BIST Detected LOW RX PLL Out of Lock {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) No Page [+] Feedback ...

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... Document #: 38-02101 Rev. *B Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0204TRB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range + 0.5V CC ...

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... LVTTL Output Test Load 3.0V 2.0V 2. 1.4V th 0.8V 0.8V GND ≤ (c) LVTTL Input Test Waveform CYV15G0204TRB AC Electrical Characteristics Parameter CYV15G0204TRB Transmitter LVTTL Switching Characteristics Over the Operating Range f TXCLKx Clock Cycle Frequency TS t TXCLKx Period=1/f TXCLK TS [16] t TXCLKx HIGH Time TXCLKH [16] t ...

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... TXCLKOx Clock Frequency = REFCLKx Frequency TOS t TXCLKOx Period=1/f TXCLKO t TXCLKO Duty Cycle centered at 60% HIGH time TXCLKOD CYV15G0204TRB Receiver LVTTL Switching Characteristics Over the Operating Range f RXCLKx± Clock Output Frequency RS t RXCLKx± Period = 1/f RXCLKP t RXCLKx± Duty Cycle Centered at 50% (Full Rate and Half Rate) ...

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... JTAG Test Clock Period TCLK CYV15G0204TRB Device RESET Characteristics Over the Operating Range t Device RESET Pulse Width RST CYV15G0204TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range Parameter t Bit Time B [16] t CML Output Rise Time 20−80% (CML Test Load) ...

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... Capacitance Parameter Description C TTL Input Capacitance INTTL C PECL input Capacitance INPECL CYV15G0204TRB HOTLink II Transmitter Switching Waveforms Transmit Interface t Write Timing TXCLKH TXCLKx selected TXCLKx TXDx[9:0] Transmit Interface Write Timing REFCLKx selected t REFH TXRATEx = 0 REFCLKx TXDx[9:0], Transmit Interface Write Timing REFCLKx selected ...

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... CYV15G0204TRB HOTLink II Transmitter Switching Waveforms Transmit Interface TXCLKOx Timing t REFH TXRATEx = 0 REFCLKx Note28 TXCLKOx Switching Waveforms for the CYV15G0204TRB HOTLink II Receiver Receive Interface Read Timing RXRATEx = 0 RXCLKx+ RXCLKx– RXDx[9:0] Receive Interface Read Timing RXRATEx = 1 RXCLKx+ RXCLKx– RXDx[9:0] Document #: 38-02101 Rev. *B ...

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... Switching Waveforms for the CYV15G0204TRB HOTLink II Receiver Bus Configuration Write Timing ADDR[3:0] DATA[6:0] WREN Document #: 38-02101 Rev WRENP t DATAS CYV15G0204TRB t DATAH Page [+] Feedback ...

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... POWER E04 VCC POWER E17 VCC POWER E18 VCC POWER E19 VCC POWER E20 VCC POWER F01 RXDC[8] LVTTL OUT CYV15G0204TRB Ball ID Signal Name Signal Type F17 NC NO CONNECT F18 NC NO CONNECT F19 TXCLKOB LVTTL OUT F20 NC NO CONNECT G01 GND ...

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... V17 NC NO CONNECT V18 NC NO CONNECT V19 NC NO CONNECT V20 NC NO CONNECT W01 VCC POWER W02 VCC POWER CYV15G0204TRB Ball ID Signal Name Signal Type L20 TXDB[6] LVTTL IN M01 RXDC[6] LVTTL OUT M02 RXDC[7] LVTTL OUT W03 LFID LVTTL OUT W04 RXCLKD– ...

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... Ordering Information Speed Ordering Code Standard CYV15G0204TRB-BGC Standard CYV15G0204TRB-BGXC Package Diagram 256-Lead L2 Ball Grid Array ( 1.57 mm) BL256 HOTLink is a registered trademark and HOTLink trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-02101 Rev. *B © ...

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... Document History Page Document Title: CYV15G0204TRB Independent Clock HOTLink II™ Dual Serializer and Dual Reclocking Deserializer Document Number: 38-02101 ISSUE REV. ECN NO. DATE ** 244348 See ECN *A 338721 See ECN *B 384307 See ECN Document #: 38-02101 Rev. *B ORIG. OF CHANGE DESCRIPTION OF CHANGE FRE New Data Sheet ...