NCV3020ADR2G ON Semiconductor, NCV3020ADR2G Datasheet - Page 20

• Manufacturer Part Number: NCV3020ADR2G
• Description: IC PWM CTLR SYNC 8SOIC
• Manufacturer: ON Semiconductor
• Series: -r

Specifications of NCV3020ADR2G

• Pwm Type: Voltage Mode
• Number Of Outputs: 1
• Frequency - Max: 360kHz
• Duty Cycle: 84%
• Voltage - Supply: 4.7 V ~ 28 V
• Buck: Yes
• Boost: No
• Flyback: No
• Inverting: No
• Doubler: No
• Divider: No
• Cuk: No
• Isolated: No
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-SOIC (0.154", 3.90mm Width)
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

delay times. Turn−on and turn−off times must be short
enough to prevent cross conduction. If not, there will be
conduction from the input through both MOSFETs to
ground. Therefore, the following conditions must be met.
be found in their appropriate datasheets for specific
conditions. NOL
were described earlier and are 85 ns and 75 ns, respectively.
Feedback and Compensation
transconductance error amplifier compensated by an
external compensation network. Compensation is needed to
achieve accurate output voltage regulation and fast transient
Table 2. COMPENSATION TYPES
t
and
t
d(ON)_CONTROL
(ON)_SYNC
Another consideration during MOSFET selection is their
The MOSFET parameters, t
The NCP3020 is a voltage mode buck convertor with a
Zero Crossover Frequency Condition
) NOL
f
f
f
P0
P0
P0
R
R
Logic Signal
Logic Signal
) NOL
LH
< f
< f
< f
DS(on)min
DS(on)min
High−Side
High−Side
Low−Side
R
R
Low−Side
MOSFET
MOSFET
HL
Z0
0
0
DSmax
DSmax
and NOL
< f
< f
< f
u t
Z0
S
LH
0
/2 < f
< f
< f
d(OFF)_CONTROL
u t
S
S
Z0
/2
/2
d(ON)
HL
d(OFF)_SYNC
t
are the dead times which
d(on)
, t
t
r
r
, t
d(OFF)
) t
Figure 34. MOSFETs Timing Diagram
) t
NOL
f _CONTROL
and t
f_SYNC
HL
f
(eq. 37)
are can
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Compensation Type
t
t
f
d(off)
Type III Method II
Type III Method I
t
d(on)
Type II
t
r
20
response. The goal of the compensation circuit is to provide
a loop gain function with the highest crossing frequency and
adequate phase margin (minimally 45°). The transfer
function of the power stage (the output LC filter) is a double
pole system. The resonance frequency of this filter is
expressed as follows:
output filter capacitor introduces a high frequency zero to
the filter network. Its value can be calculated by using the
following equation:
to be 1/10 − 1/5 of the switching frequency. Table 2 shows
the three methods of compensation.
Parasitic Equivalent Series Resistance (ESR) of the
The main loop zero crossover frequency f
NOL
t
d(off)
LH
t
f
f
Z0
f
P0
+
+
Typical Output Capacitor Type
2 @ p @ C
2 @ p @ L @ C
Electrolytic, Tantalum
Tantalum, Ceramic
OUT
1
1
Ceramic
@ ESR
OUT
0
can be chosen
(eq. 39)
(eq. 38)