DS33ZH11+ Maxim Integrated Products, DS33ZH11+ Datasheet - Page 41

• Manufacturer Part Number: DS33ZH11+
• Description: IC MAPPER ETHERNET 100CSBGA
• Manufacturer: Maxim Integrated Products

Specifications of DS33ZH11+

• Applications: Data Transport
• Interface: Serial
• Voltage - Supply: 1.8V, 2.5V, 3.3V
• Package / Case: 100-LBGA
• Mounting Type: Surface Mount
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DS33Z11 Ethernet Mapper
8.12.1 Full-Duplex Flow Control
In the software mode automatic flow control is enabled by default. The host processor can disable this
functionality with SU.GCR.ATFLOW. In hardware mode, the user must apply a logic high level to the AFCS pin to
enable automatic flow control. The flow control mechanism is governed by the high watermarks (SU.RQHT). The
SU.RQLT low threshold can be used as indication that the network congestion is clearing up. The value of
SU.RQLT does not affect the flow control. When the connection queue high threshold is exceeded the DS33Z11
will send a pause frame with the timer value programmed by the user. See
Table 8-6
for more information. It is
recommended that 80 slots (80 by 64 bytes or 5120 bytes) be used as the standard timer value.
The pause frame causes the distant transmitter to “pause for a time” before starting transmission again. The
pause command has a multicast address 01-80-62-00-00-01. The high and low thresholds for the receive queue
are configurable by the user but it is recommended that the high threshold be set approximately 96 packets from
the maximum size of the queue and the low threshold 96 packets lower than the high threshold. The DS33Z11
will send a pause frame as the queue has crossed the high threshold and a frame is received. Pause is sent
every time a frame is received in the “high threshold state”. Pause control will only take care of temporary
congestion. Pause control does not take care of systems where the traffic throughput is too high for the queue
sizes selected. If the flow control is not effective the receive queue will eventually overflow. This is indicated by
SU.QCRLS.RQOVFL latched bit. If the receive queue is overflowed any new frames will not be received.
The user has the option of not enabling automatic flow control. In this case the thresholds and corresponding
interrupt mechanism to send pause frame by writing to flow control busy bit in the MAC flow control registers
SU.MACFCR.FCB, SU.GCR.JAME, and SU.MACFCR. This allows the user to set not only the watermarks but
also to decide when to send a pause frame or not based on watermark crossings.
On the receive side the user has control over whether to respond to the pause frame sent by the distant end (PCF
bit). Note that if automatic flow control is enabled the user cannot modify the FCE bit in the MAC flow control
register. On the Transmit queue the user has the option of setting high and low thresholds and corresponding
interrupts. There is no automatic flow control mechanism for data received from the Serial side waiting for
transmission over the Ethernet interface during times of heavy Ethernet congestion.
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