ADM1025ARQ-REEL7 ON Semiconductor, ADM1025ARQ-REEL7 Datasheet - Page 13

• Manufacturer Part Number: ADM1025ARQ-REEL7
• Description: IC MONITOR SYS/VOLT 5CH 16QSOP
• Manufacturer: ON Semiconductor

Specifications of ADM1025ARQ-REEL7

• Rohs Status: RoHS non-compliant
• Applications: PC's, PDA's
• Interface: I²C
• Voltage - Supply: 3 V ~ 5.5 V
• Package / Case: 16-QSOP
• Mounting Type: Surface Mount

USING THE ADM1025/ADM1025A
Power-On RESET
When power is first applied, the ADM1025/ADM1025A performs
a “power- on reset” on several of its registers. Registers whose
power-on values are not shown have power-on conditions that
are indeterminate. Value and limit registers are reset to 00h on
power-up. The ADC is inactive. In most applications, usually
the first action after power-on would be to write limits into the
Limit Registers.
Power-on reset clears or initializes the following registers
(the initialized values are shown in Table VI):
– Configuration Register
– Status Registers #1 and #2
– VID0-3 Register
– VID4 Register
– Test Register
INITIALIZATION
Configuration Register Initialization performs a similar, but not
identical, function to power-on reset.
Configuration Register Initialization is accomplished by setting
Bit 7 of the Configuration Register high. This bit automatically
clears after being set.
USING THE CONFIGURATION REGISTER
Control of the ADM1025/ADM1025A is provided through the
configuration register. The Configuration Register is used to
start and stop the ADM1025/ADM1025A, program the operating
modes of Pins 11 and 16, and provide the initialization function
described above.
Bit 0 of the Configuration Register controls the monitoring loop
of the ADM1025/ADM1025A. Setting Bit 0 low stops the
monitoring loop and puts the ADM1025/ADM1025A into a
low power mode thereby reducing power consumption. Serial
bus communication is still possible with any register in the
ADM1025/ADM1025A while in low power mode. Setting Bit 0
high starts the monitoring loop.
Bit 4 of the Configuration Register causes a low going 20 ms (typ)
pulse at the RST pin (Pin 16) when set. This bit is self-clearing.
Bit 5 of the Configuration Register selects the operating mode of
Pin 11 between the default of 12 V analog input (Bit 5 = 0) and
VID4 (Bit 5 = 1).
Bit 7 of the Configuration Register is used to start a Configura-
tion Register Initialization when it is set to 1.
USING THE OFFSET REGISTER
This register contains a twos complement value that is added
(or subtracted if the number is negative) to either the internal or
external temperature reading. Note that the default value in the
offset register is zero, so zero is always added to the temperature
reading. The offset register is configured for the external tem-
perature channel by default. It may be switched to the internal
channel by setting Bit 0 of the Test Register to 1, setting Bit 6 of
the VID Register to 1, and clearing Bit 7 of the VID Register.
STARTING CONVERSION
The monitoring function of the ADM1025/ADM1025A is started by
writing to the Configuration Register and setting Start (Bit 0) high.
Limit values should be written into the Limit Registers before
REV. C
–13–
starting the ADC to avoid spurious out-of-limit conditions. The
time taken to complete the analog measurements depends on
how they are configured, as described elsewhere. Once the
measurements have been completed, the results can be read from
the Value Registers at any time.
REDUCED POWER AND SHUTDOWN MODE
The ADM1025/ADM1025A can be placed in a low power mode
by setting Bit 0 of the Configuration Register to 0. This disables
the internal ADC. Full shutdown mode may then be achieved
by setting Bit 7 of the VID Register to 1 and Bit 0 of the Test
Register to 1. This turns off power to all analog circuits and stops
the monitoring cycle, if running, but it does not affect the
condition of any of the registers. The device will return to its
previous state when these bits are reset to zero.
5 V OPERATION
The ADM1025/ADM1025A may be operated with V
to any supply voltage between 3.0 V and 5.5 V, but it should be
noted that the device has been optimized for 3.3 V operation. In
particular, the internal voltage divider used to measure the supply
voltage is optimized for 3.3 V. Powering the device from 5 V will
cause the V
this case, the 5 V measurement should be read from the 5 V
Reading Register (Register 23h), instead of the V
Register. Note also that when the 12 V
to read VID4, due to its internal voltage divider, it will only read
V
being powered from the 3.3 V supply.
REGISTERS
Bit
7–0
Register
Name
Configuration Register
Status Register 1
Status Register 2
VID Register
VID4 Register
Value and Limit
Company ID
Stepping
IH
Registers
= 2.1 V on the 12 V
Name
Address Pointer
CC
Table V. Address POINTER Register
Reading Register (Register 25h) to overrange. In
Table VI. List of Registers
IN
/VID4 pin as logic high if the device is
R/W
Write
Address
A7–A0
in Hex
40h
41h
42h
47h
49h
15–3Dh
3Eh
3Fh
ADM1025/ADM1025A
Address of ADM1025/
Description
ADM1025A Registers. See
the tables below for detail.
IN
/VID4 pin is programmed
Power On
Value of
Registers: <7:0>
0000 1000
0000 0000
0000 0000
<7:4> = 0000, <3:0> =
VID3–VID0
<0> = VID4; Default =
1000 000 (VID4)
0100 0001
0010 (Bits 3:0 Version
Number)
CC
CC
Reading
connected