ADG412BRZ Analog Devices Inc, ADG412BRZ Datasheet - Page 10

• Manufacturer Part Number: ADG412BRZ
• Description: IC SWITCH QUAD SPST 16SOIC
• Manufacturer: Analog Devices Inc
• Series: LC²MOSr

Specifications of ADG412BRZ

• Design Resources: Parametric Measurement Unit and Supporting Components for PAD Appls Using AD5522 and AD7685 (CN0104)
• Function: Switch
• Circuit: 4 x SPST - NO
• On-state Resistance: 35 Ohm
• Voltage Supply Source: Single, Dual Supply
• Voltage - Supply, Single/dual (±): 12V, ±15V
• Current - Supply: 1µA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 16-SOIC (0.154", 3.90mm Width)
• Analog Switch Type: SPST
• No. Of Channels: 4
• On State Resistance Max: 25ohm
• Turn Off Time: 100ns
• Turn On Time: 110ns
• Supply Voltage Range: 4.5V To 5.5V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADG411/ADG412/ADG413
APPLICATIONS
Figure 13 illustrates a precise, fast, sample-and-hold circuit. An
AD845 is used as the input buffer while the output operational
amplifier is an AD711. During the track mode, SW1 is closed
and the output V
mode, SW1 is opened and the signal is held by the hold
capacitor C
Due to switch and capacitor leakage, the voltage on the hold
capacitor decreases with time. The ADG411/ADG412/ADG413
minimizes this droop due to its low leakage specifications. The
droop rate is further minimized by the use of a polystyrene
hold capacitor. The droop rate for the circuit shown is typically
30 μV/μs.
A second switch, SW2, which operates in parallel with SW1, is
included in this circuit to reduce pedestal error. Since both
switches are at the same potential, they have a differential effect
on the op amp AD711, which minimizes charge injection
effects. Pedestal error is also reduced by the compensation
network R
C
H
and C
.
OUT
C
. This compensation network also reduces
follows the input signal V
IN
. In the hold
Rev. D | Page 10 of 16
the hold time glitch while optimizing the acquisition time.
Using the illustrated op amps and component values, the
pedestal error has a maximum value of 5 mV over the ±10 V
input range. Both the acquisition and settling times are 850 ns.
V
IN
AD845
+15V
–15V
Figure 13. Fast, Accurate Sample-and-Hold
S
S
+15V
SW1
SW2
ADG411
ADG412
ADG413
–15V
+5V
D
D
75 Ω
R
C
2200pF
2200pF
C
1000pF
C
C
H
AD711
+15V
–15V
V
OUT