SI4705-D60-GU Silicon Laboratories Inc, SI4705-D60-GU Datasheet
SI4705-D60-GU
Specifications of SI4705-D60-GU
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SI4705-D60-GU Summary of contents
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... FM digital tuning EN55020 compliant No manual alignment necessary Programmable reference clock Adjustable soft mute control RDS/RBDS processor (Si4705-D60) Digital audio out 2-wire and 3-wire control interface Integrated LDO regulator QFN and SSOP packages ...
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Si4704/05-D60 2 Rev. 1.0 ...
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... Stereo Audio Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.7. Received Signal Qualifiers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.8. Volume Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.9. Stereo DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 4.10. Soft Mute . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.11. FM Hi-Cut Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 4.12. De-emphasis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.13. RDS/RBDS Processor (Si4705-D60 Only .24 4.14. Tuning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.15. Seek . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.16. Reference Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 4.17. Control Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.18. GPO Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 4.19. Firmware Upgrades . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 4 ...
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Si4704/05-D60 9. PCB Land Pattern . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Electrical Specifications Table 1. Recommended Operating Conditions Parameter Analog Supply Voltage Digital and I/O Supply Voltage Power Supply Powerup Rise Time Interface Power Supply Powerup Rise Time Ambient Temperature Notes: 1. All minimum and maximum specifications apply across the ...
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Si4704/05-D60 Table 3. DC Characteristics (V = 2 1. Parameter FM Mode V Supply Current AQFN V Supply Current DQFN V Supply Current ASSOP V Supply Current DSSOP ...
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Table 4. Reset Timing Characteristics (V = 2 1. Parameter RST Pulse Width and GPO1, GPO2/INT Setup to RST GPO1, GPO2/INT Hold from RST Important Notes: 1. When ...
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Si4704/05-D60 Table 5. 2-Wire Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK Low Time SCLK High Time SCLK Input to SDIO Setup (START) ...
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SU:STA HD:STA LOW 70% SCLK 30% 70% SDIO 30% START t r:IN Figure 2. 2-Wire Control Interface Read and Write Timing Parameters SCLK A6-A0, SDIO R/W START ADDRESS + R/W Figure 3. 2-Wire Control Interface Read and ...
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Si4704/05-D60 Table 6. 3-Wire Control Interface Characteristics (V = 2 1. Parameter SCLK Frequency SCLK High Time SCLK Low Time SDIO Input, SEN to SCLKSetup SDIO Input to ...
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Table 7. Digital Audio Interface Characteristics (V = 2 1. Parameter DCLK Cycle Time DCLK Pulse Width High DCLK Pulse Width Low DFS Set-up Time to DCLK Rising ...
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Si4704/05-D60 Table 8. FM Receiver Characteristics (V = 2 1. Parameter Input Frequency 3,4,5,6 Sensitivity 6,7 RDS Sensitivity 7,8 LNA Input Resistance 7,8 LNA Input Capacitance 7,9 Input ...
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Table 8. FM Receiver Characteristics (V = 2 1. Parameter 3,4,5,6,7,11,12 Intermod Sensitivity 7,14 Audio Output Load Resistance 7,14 Audio Output Load Capacitance 7 Seek/Tune Time 7 Powerup ...
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Si4704/05-D60 Table 9. 64–75.9 MHz Input Frequency FM Receiver Characteristics (V = 2 1. Parameter Input Frequency , 4,5,6 8 Sensitivity 3,7 LNA Input Resistance 3,7 LNA Input ...
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Table 10. AC Receiver Characteristics—AUXIN Analog to Digital Converter (V = 2 1. Parameter Symbol Total Harmonic Distortion + Noise Dynamic Range/Signal to Noise Ratio Crosstalk Gain Mismatch ...
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Si4704/05-D60 Table 12. Reference Clock and Crystal Characteristics (V = 2 1. Parameter 1 RCLK Supported Frequencies 2 RCLK Frequency Tolerance REFCLK_PRESCALE REFCLK Crystal Oscillator Frequency 2 Crystal ...
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Typical Application Schematic 2.1. QFN Typical Application Schematic 16 C7 DFS LIN 15 C8 DOUT RIN R3 17 GP03/DCLK DCLK R2 14 LOUT DFS R1 13 ROUT DOUT Si4704/05 C9 Optional: AUXIN/Digital Audio Out OPMODE: 0x5B, 0x0B C2 FM ...
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Si4704/05-D60 2.2. SSOP Typical Application Schematic Optional: Digital Audio Out OPMODE: 0xB0, 0xB5 C9 R1 DOUT R2 DFS R3 GPO3/DCLK GPO2/INT GPO1 C2 FM Antenna Embedded Antenna Notes: 1. Place C1 close to VA and C4 close to VD pin. ...
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Bill of Materials 3.1. QFN/SSOP Bill of Materials Table 13. Si4704/05-D60 QFN/SSOP Bill of Materials Component(s) C1 Supply bypass capacitor, 22 nF, ±20%, Z5U/X7R C2 Coupling capacitor, 1 nF, ±20%, Z5U/X7R C4 Supply bypass capacitor, 100 nF, 10%, Z5U/X7R ...
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... The Si4705-D60 incorporates a digital signal processor for the European Radio Data System (RDS) and the North American Radio Broadcast Data System (RBDS) including ...
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Operating Modes The Si4704/05-D60 operates in either an FM receive or audio AUXIN ADC mode mode, radio signals are received on FMI and processed by the FM front-end circuitry. In audio AUXIN ADC mode, stereo audio signals ...
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Si4704/05-D60 INVERTED (OFALL = 1) DCLK DCLK (OFALL = 0) DFS (OMODE = 0000) 1 DCLK DOUT 1 2 MSB INVERTED (OFALL = 1) DCLK (OFALL = 0) DCLK DFS Left-Justified (OMODE = 0110) DOUT 1 2 ...
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Stereo Audio Processing The output of the FM demodulator is a stereo multiplexed (MPX) signal. The MPX standard was developed in 1961, and is used worldwide. Today's MPX signal format consists of left + right (L+R) audio, left – ...
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... FM_DEEMPHASIS property. 4.13. RDS/RBDS Processor (Si4705-D60 Only) The Si4705-D60 implements an RDS/RBDS* processor for symbol decoding, block synchronization, error detection, and error correction. The Si4705-D60 device is user configurable and provides an optional interrupt synchronized, loses synchronization, and/or the user configurable RDS FIFO threshold has been met. ...
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Control Interface A serial port slave interface is provided, which allows an external controller to send commands to the Si4704/05- D60 and receive responses from the device. The serial port can operate in two bus modes: 2-wire mode and ...
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Si4704/05-D60 4.18. GPO Outputs The Si4704/05-D60 provides three general-purpose output pins. The GPO pins can be configured to output a constant low, constant high, or high-impedance. The GPO pins can be reconfigured as specialized functions. 4.19. Firmware Upgrades The Si4704/05-D60 ...
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Pin Descriptions 5.1. Si4704/05-D60-GM RFGND Pin Number(s) Name connect. Leave floating. 2 FMI FM RF inputs. FMI should be connected to the antenna trace. 3 RFGND RF ground. Connect to ground plane on PCB. 4 ...
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Si4704/05-D60 5.2. Si4704/05-D60-GU Pin Number(s) Name 1 DOUT/[RIN] Digital output data for digital output mode or Right channel input for AUX IN ADC mode. 2 DFS/[LIN] Digital frame synchronization input for digital output mode or Left channel input for AUXIN ...
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... Part Number Si4704-D60-GM FM Broadcast Radio Receiver 2 Si4704-D60-GU Si4705-D60-GM FM Broadcast Radio Receiver with 2 RDS/RBDS Si4705-D60-GU Notes: 1. Add an “(R)” at the end of the device part number to denote tape and reel option. 2. SSOP devices operate down to V Description = °C. A Rev. 1.0 Si4704/05-D60 Package Operating ...
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... Circle = 0.5 mm Diameter Line 3 Marking: (Bottom-Left Justified Year WW = Workweek 30 0560 DTTT YWW 04 = Si4704 Si4705-D60 Firmware Revision 6. Revision D Die. Internal tracking code. Pin 1 Identifier. Assigned by the Assembly House. Corresponds to the last significant digit of the year and work week of the mold date. Rev. 1.0 ...
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... Mark Method: Part Number Die Revision Line 1 Marking: Firmware Revision Package Type YY = Year WW = Work week Line 2 Marking: TTTTTT = Manufacturing code 470XD60GU YYWWTTTTTT 4704 = Si4704; 4705 = Si4705-D60 Revision D die Firmware Revision 6. 24-pin SSOP Pb-free package Assigned by the Assembly House. Rev. 1.0 Si4704/05-D60 31 ...
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Si4704/05-D60 8. Package Outline 8.1. Si4704/05-D60 QFN Figure 12 illustrates the package details for the Si4704/05-D60. Table 15 lists the values for the dimensions shown in the illustration. Figure 12. 20-Pin Quad Flat No-Lead (QFN) Symbol Millimeters Min Nom A ...
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Si4704/05-D60 SSOP Figure 13 illustrates the package details for the Si4704/05-D60. Table 16 lists the values for the dimensions shown in the illustration. Dimension θ aaa bbb ccc ddd ...
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Si4704/05-D60 9. PCB Land Pattern 9.1. Si4704/05-D60 QFN Figure 14 illustrates the PCB land pattern details for the Si4704/05-D60-GM QFN. Table 17 lists the values for the dimensions shown in the illustration. 34 Figure 14. PCB Land Pattern Rev. 1.0 ...
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Table 17. PCB Land Pattern Dimensions Symbol Millimeters Min Max D 2.71 REF D2 1.60 1.80 e 0.50 BSC E 2.71 REF E2 1.60 1.80 f 2.53 BSC GD 2.10 — Notes: General 1. All dimensions shown are in millimeters ...
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Si4704/05-D60 9.2. Si4704/05-D60 SSOP Figure 15 illustrates the PCB land pattern details for the Si4704/05-D60-GU SSOP. Table 18 lists the values for the dimensions shown in the illustration. Table 18. PCB Land Pattern Dimensions Dimension ...
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Additional Reference Resources Contact your local sales representatives for more information or to obtain copies of the following references: EN55020 Compliance Test Certificate AN332: Si47xx Programming Guide AN383: Si47xx Antenna, Schematic, Layout, and Design Guidelines AN388: ...
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Si4704/05-D60 N : OTES 38 Rev. 1.0 ...
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Si4704/05-D60 OCUMENT HANGE IST Revision 0.4 to Revision 1.0 Updated application schematic. Updated pin descriptions. Rev. 1.0 ...
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