IC MULTIPLEXER TRPL 2X1 24TSSOP

AD8185ARUZ

Manufacturer Part NumberAD8185ARUZ
DescriptionIC MULTIPLEXER TRPL 2X1 24TSSOP
ManufacturerAnalog Devices Inc
AD8185ARUZ datasheet
 


Specifications of AD8185ARUZ

FunctionMultiplexerCircuit3 x 2:1
Voltage Supply SourceDual SupplyVoltage - Supply, Single/dual (±)±4.5 V ~ 5.5 V
Current - Supply25mAOperating Temperature-40°C ~ 85°C
Mounting TypeSurface MountPackage / Case24-TSSOP (0.173", 4.40mm Width)
No. Of Circuits3Supply Current25mA
Supply Voltage Range± 4.5V To ± 5.5VOperating Temperature Range-40°C To +85°C
Analog Switch Case StyleTSSOPNo. Of Pins24
Lead Free Status / RoHS StatusLead free / RoHS Compliant  
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AD8183/AD8185
result, the input and output traces, in addition to having a con-
trolled impedance, are well shielded.
SEL A/B AND OE
SEL A/B (Pin 22 of the device) allows the A or B inputs to be
selected.
When SEL A/B is at logic low, (equal to or less than 0.8 V),
inputs 0A, 1A and 2A are directed to OUTPUTs 0, 1, and 2,
respectively. When SEL A/B is at logic high, (equal to or greater
than 2.0 V), inputs 0B, 1B, and 2B are directed to OUTPUTs
0, 1, and 2, respectively.
There are two ways to provide SEL A/B to the device: using a
jumper or a BNC connection. With the jumper in the W4 posi-
tion, SEL A/B is tied to ground. This selects the A inputs.
With the jumper in the W3 position, SEL A/B is tied to 5 V,
through pull up resistor R15. This selects the B inputs.
If faster use of SEL A/B is desired, the 50
J10 can be used. If J10 is used, there must NOT be a jumper on
W3 and W4. Microstrip line techniques provide a 50
teristic impedance from J10 to the device. Please refer to Figure
OE
OE
J11
75
STRIPLINE
IN0A
J1
R1
75
AGND
75
STRIPLINE
IN1A
J2
R2
75
AGND
75
STRIPLINE
IN2A
J3
R3
V
CC
75
V
EE
C7
C8
AGND
0.01 F
0.01 F
AGND
AGND
75
STRIPLINE
IN2B
J4
R4
75
AGND
75
STRIPLINE
IN1B
J5
R5
75
AGND
75
STRIPLINE
IN0B
J6
R6
75
AGND
41 for the arrangement of the PCB layers. If J10 is used, the
user may wish to install a 50
OE (Pin 23 of the device) allows the three outputs to be enabled
or disabled. When OE is at logic low, (equal to or less than
0.8 V), Outputs 0, 1, and 2 are enabled. When OE is at logic
high, (equal to or greater than 2.0 V), Outputs 0, 1, and 2 are
disabled (placed into a high impedance state).
Once again, there are two different ways to provide OE to the
device: using a jumper or a BNC connection. With the jumper
in the W2 position, OE is tied to ground. This enables the outputs.
With the jumper in the W1 position, OE is tied to 5 V, through
pull-up resistor R16. This selects “Hi Z,” or high impedance,
and the outputs are disabled.
If faster use of OE is desired, the 50
can be used. If J11 is used, there must NOT be a jumper on W1
and W2. Microstrip line techniques provide a 50
tic impedance from J11 to the device. Please refer to Figure 41
BNC connector at
for the arrangement of the PCB layers. If J11 is used, the user
may wish to install a 50
charac-
DVCC
DVCC
P1
1
+
C3
C6
10 F
0.1 F
DGND
DGND
DGND
DGND
P1
2
V
EE
V
P1
4
EE
C2
C5
+
10 F
0.1 F
AGND
AGND
AGND
AGND
P1
5
V
CC
V
V
P1
6
CC
CC
+
C1
C4
10 F
0.1 F
R16
20k
AGND
AGND
W1
W2
DGND
50
MICROSTRIP LINE
R11
50
OPTIONAL
DGND
V
CC
C15
0.01 F
AGND
DUT
1
24
V
IN0A
CC
2
23
OE
DGND
DGND
3
22
SEL A/B
IN1A
4
21
AGND
AGND
V
CC
5
20
IN2A
OUT0
6
19
AD8183/
V
V
CC
EE
7
AD8185
18
OUT1
V
EE
8
17
V
IN2B
CC
9
16
AGND
OUT2
AGND
15
10
V
IN1B
EE
14
11
DVCC
AGND
AGND
12
13
V
IN0B
CC
C9
C10
0.01 F
0.01 F
W5
AGND
DGND
AGND
DGND
Figure 42. Evaluation Board Schematic
–12–
termination resistor at R10.
BNC connector at J11
characteris-
termination resistor at R11.
DVCC
DGND
V
EE
AGND
V
V
CC
CC
R15
20k
W3
W4
SEL A/B
DGND
50
MICROSTRIP LINE
SEL A/B
J10
R10
50
OPTIONAL
DGND
V
CC
C14
0.01 F
AGND
R14
75
75
STRIPLINE
J9
OUT0
V
EE
C13
0.01 F
R13
AGND
75
75
STRIPLINE
J8
OUT1
V
CC
C12
0.01 F
R12
AGND
75
75
STRIPLINE
J7
OUT2
V
EE
DVCC
V
CC
C11
0.01 F
AGND
REV. 0