LFXP2-17E-6FN484I Lattice, LFXP2-17E-6FN484I Datasheet - Page 35

• Manufacturer Part Number: LFXP2-17E-6FN484I
• Description: IC FPGA 17KLUTS 358I/O 484-BGA
• Manufacturer: Lattice

Specifications of LFXP2-17E-6FN484I

• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Lattice Semiconductor
DLL Calibrated DQS Delay Block
Source synchronous interfaces generally require the input clock to be adjusted in order to correctly capture data at
the input register. For most interfaces a PLL is used for this adjustment. However, in DDR memories the clock,
referred to as DQS, is not free-running, and this approach cannot be used. The DQS Delay block provides the
required clock alignment for DDR memory interfaces.
The DQS signal (selected PIOs only, as shown in Figure 2-30) feeds from the PAD through a DQS delay element to
a dedicated DQS routing resource. The DQS signal also feeds polarity control logic which controls the polarity of
the clock to the sync registers in the input register blocks. Figure 2-30 and Figure 2-31 show how the DQS transi-
tion signals are routed to the PIOs.
The temperature, voltage and process variations of the DQS delay block are compensated by a set of 6-bit bus cal-
ibration signals from two dedicated DLLs (DDR_DLL) on opposite sides of the device. Each DLL compensates
DQS delays in its half of the device as shown in Figure 2-30. The DLL loop is compensated for temperature, volt-
age and process variations by the system clock and feedback loop.
Figure 2-30. Edge Clock, DLL Calibration and DQS Local Bus Distribution
Spans 16 PIOs
Left & Right Sides
Spans 18 PIOs
Top & Bottom
Sides
DQS Input
DDR_DLL
(Left)
I/O Bank 0
I/O Bank 5
2-32
I/O Bank 1
I/O Bank 4
DDR_DLL
(Right)
LatticeXP2 Family Data Sheet
ECLK1
ECLK2
Delayed
DQS
Polarity Control
DQSXFER
DQS Delay
Control Bus
Architecture