PALCE20V8-10PC Cypress Semiconductor Corp, PALCE20V8-10PC Datasheet - Page 3

• Manufacturer Part Number: PALCE20V8-10PC
• Manufacturer: Cypress Semiconductor Corp

Specifications of PALCE20V8-10PC

• Family Name: Pal®
• Process Technology: EECMOS
• # Macrocells: 8
• # I/os (max): 8
• Frequency (max): 62.5MHz
• Propagation Delay Time: 10ns
• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Supply Current: 115mA
• Operating Temp Range: 0C to 75C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 24
• Package Type: PDIP
• Lead Free Status / Rohs Status: Not Compliant

Document #: 38-03026 Rev. *B
Functional Description
The PALCE20V8 features 8 product terms per output and 40
input terms into the AND array. The first product term in a
macrocell can be used either as an internal output enable
control or as a data product term.
There are a total of 18 architecture bits in the PALCE20V8
macrocell; two are global bits that apply to all macrocells and
16 that apply locally, two bits per macrocell. The architecture
bits determine whether the macrocell functions as a register or
combinatorial with inverting or noninverting output. The output
enable control can come from an external pin or internally from
a product term. The output can also be permanently enabled,
functioning as a dedicated output or permanently disabled,
functioning as a dedicated input. Feedback paths are
selectable from either the input/output pin associated with the
macrocell, the input/output pin associated with an adjacent
pin, or from the macrocell register itself.
Power-Up Reset
All registers in the PALCE20V8 power-up to a logic LOW for
predictable system initialization. For each register, the
associated output pin will be HIGH due to active-LOW outputs.
Configuration Table
Macrocell
CG
0
0
1
1
1
0
CG
1
1
0
0
1
1
1 1
0
1
CL0
X
0
0
1
0
1
1
x
V
Registered Output
Combinatorial I/O
Combinatorial Output
Input
Combinatorial I/O
CC
CL1
USE ULTRA37000
CG
x
1
ALL NEW DESIGNS
Cell Configuration
CL0
x
CLK
CG
CG
0
for pin 15 and 22 (DIP)
1
for pin 16 to 21 (DIP)
D
Electronic Signature
An electronic signature word is provided in the PALCE20V8
that consists of 64 bits of programmable memory that can
contain user-defined data.
Security Bit
A security bit is provided that defeats the readback of the
internal programmed pattern when the bit is programmed.
Low Power
The Cypress PALCE20V8 provides low-power operation
through the use of CMOS technology, and increased testability
with Flash reprogrammability.
Product Term Disable
Product Term Disable (PTD) fuses are included for each
product term. The PTD fuses allow each product term to be
individually disabled.
Input and I/O Pin Pull-Ups
The PALCE20V8 input and I/O pins have built-in active
pull-ups that will float unused inputs and I/Os to an active HIGH
state (logical 1). All unused inputs and three-stated I/O pins
should be connected to another active input, V
to improve noise immunity and reduce I
Q
Q
TM
V
CC
OE
FOR
Registered Med PALs
Registered Med PALs
Small PALs
Small PALs
20L8 only
1 1
0
1
1 1
1
0 0
0
1
1
0
X
0
0
1
0
1
X
CL0
Devices Emulated
x
Macrocell
Adjacent
From
Adjacent
Pin
To
CC
PALCE20V8
.
I/O
CC
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x
, or Ground
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