W320-04X Silicon Laboratories Inc, W320-04X Datasheet
W320-04X
Specifications of W320-04X
Available stocks
Related parts for W320-04X
W320-04X Summary of contents
Page 1
... CPU#0:2 VDD_PCI PCI_F0:2 Stop Clock PCI0:6 Control VDD_3V66 3V66_0 3V66_2:4/ 66BUFF0:2 3V66_5/ 66IN VDD_48MHz USB (48MHz) DOT (48MHz) VCH_CLK/ 3V66_1 Tel:(408) 855-0555 Fax:(408) 855-0550 W320-04 ® processors using SSOP and TSSOP Top View REF VDD_REF XTAL_IN 2 55 XTAL_OUT GND_REF ...
Page 2
... S[2:0] and MULTI0 inputs are valid and sampled (Active LOW). Once PWRGD# is sampled LOW, the status of this output will be ignored. SMBus compatible SDATA. SMBus compatible SCLK. 3.3V power supply for outputs. 3.3V power supply for 48 MHz. 3.3V power supply for PLL. Ground for PLL. W320-04 Page ...
Page 3
... Type 3B 12 CPU CPU# 3V66 66BUFF IREF*2 FLOAT LOW LOW ON FLOAT LOW W320-04 USB/DOT REF0(MHz) (MHz) Notes 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz 14.318 MHz 48 MHz ...
Page 4
... SMBus interface is provided according to SMBus specification. Through the Serial Data Interface, various device functions such as individual clock output buffers, can be individually enabled or disabled. W320-04 supports both block read and block write operations. The registers associated with the Serial Data Interface initialize to their default setting upon power-up, and therefore use of this interface is optional ...
Page 5
... Free running Stopped with PCI_STOP# Allow control of PCI_F1 with assertion of PCI_STOP Free running Stopped with PCI_STOP# Allow control of PCI_F0 with assertion of PCI_STOP Free running Stopped with PCI_STOP# PCI_F2 Output Enable PCI_F1Output Enable PCI_F0 Output Enable W320-04 Power On Type Default R N/A R/W 0 ...
Page 6
... Buffered 1 Output Enable 1 = Enabled Disabled 66-MHz Buffered 0 Output Enable 1 = Enabled Disabled Pin Description N/A N/A Tpd 66IN to 66BUFF propagation delay control DOT edge rate control USB edge rate control Description W320-04 Power On Type Default R/W 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W ...
Page 7
... For I =6*IRef Configuration OH REF, DOT, USB 3V66, DOT, PCI, REF REF, DOT, USB 3V66, PCI, REF Three-state = 133 MHz CPU VDD_CORE/VDD3.3 = 3.465V and @ IREF = 2.32 mA VDD_CORE/VDD3.3 = 3.465V and @ IREF = 5.0 mA W320-04 Min. Max. Unit 3.135 3.465 V 2.85 3.465 V ° 22.5 ...
Page 8
... Measured single ended waveform from 0.175V to 0.525V Measured at Crossover Measured at Crossover t With all outputs running Measured with test loads Measured with test loads Measured with test loads Measured with test loads = 2.5V, duty cycle is measured at 1.25V. DD W320-04 Min. Max 0.5 2.0 1.0 4.0 500 175 500 1 ...
Page 9
... Definition and Application of PWRGD# Signal Vtt VRM8.5 PWRGD# S0 CLOCK GENERATOR S1 Rev 1.0, November 25, 2006 PWRGD# BSEL0 3.3V 3.3V NPN 10K 10K W320-04 CPU BSEL1 3.3V 10K GMCH 10K Page ...
Page 10
... Duty Cycle Timing (Single-ended Output Duty Cycle Timing (CPU Differential Output All Outputs Rise/Fall Time OUTPUT t 2 CPU-CPU Clock Skew Host_b Host Host_b Host t 4 3V66-3V66 Clock Skew 3V66 3V66 t PCI-PCI Clock Skew PCI PCI t Rev 1.0, November 25, 2006 W320-04 Page ...
Page 11
... PCI t 7 CPU Clock Cycle-Cycle Jitter Host_b Host Cycle-Cycle Clock Jitter CLK PWRDWN# Assertion 66BUFF PCI PCI_F (APIC) PWR_DWN# CPU CPU# 3V66 66IN USB REF Note: PCI_STOP# asserted LOW Rev 1.0, November 25, 2006 Power Down Rest of Generator W320-04 UNDEF Page ...
Page 12
... GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM NPN VCC CPU CORE PWRGD# VCC W320 CLOCK GEN State 0 CLOCK STATE OFF CLOCK VCO OFF CLOCK OUTPUTS Rev 1.0, November 25, 2006 10-30 μs min. 100-200 μs max. ...
Page 13
... GND VRM 5/12V PWRGD# VID [3:0] BSEL [1:0] PWRGD# FROM VRM PWRGD# FROM NPN VCC CPU CORE PWRGD# 0.2 – 0.3 ms Wait for VCC W320 CLOCK delay PWRGD# GEN State 1 State 0 CLOCK STATE OFF CLOCK VCO OFF CLOCK OUTPUTS Rev 1.0, November 25, 2006 ...
Page 14
... FB = Dale ILB1206 - 300 or 2TDKACB2012L-120 or 2 Murata BLM21B601S. Ceramic Caps C1 = 10–22 µF = VIA to GND plane layer. G Note: Each supply plane or strip should have a ferrite bead and capacitors. Rev 1.0, November 25, 2006 VDDQ3 10 μ 0.005 μ 0.1 μ μF = VIA to respective supply plane layer. V W320- VDDQ3 8 Ω Page ...
Page 15
... R VDD_REF, VDD_PCI, VDD_3V66, VDD_CORE VDD_48 MHz, VDD_CPU Test Node Test Node 30 pF Ordering Information Ordering Code W320-04H W320-04HT W320-04X W320-04XT Lead-Free CYW320OXC-4 CYW320OXC-4T CYW320ZXC-4 CYW320ZXC-4T Rev 1.0, November 25, 2006 4, 9, 15, 20, 27, 31, 36 14, 19, 26, 32, 37, 46, 50 W320-04 Ref,USB Outputs 20 pF ...
Page 16
... MAX. 0.20[0.008] 0.051[0.002] 0.152[0.006] 0.170[0.006] SEATING 0.279[0.011] PLANE W320-04 DIMENSIONS IN INCHES MIN. MAX. 0.005 .010 0.010 0.024 0.040 0°-8° DIMENSIONS IN MM[INCHES] MIN. MAX. REFERENCE JEDEC MO-153 PACKAGE WEIGHT 0.42gms PART # Z5624 STANDARD PKG. ZZ5624 LEAD FREE PKG. ...