AM29F040-120JC AMD (ADVANCED MICRO DEVICES), AM29F040-120JC Datasheet - Page 12

• Manufacturer Part Number: AM29F040-120JC
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM29F040-120JC

• Lead Free Status / Rohs Status: Not Compliant

See Figure 12 for the Data Polling timing specifications
and diagrams.
DQ6
Toggle Bit
The Am29F040 also features the “Toggle Bit” as a
method to indicate to the host system that the Embed-
ded Algorithms are in progress or completed.
During an Embedded Program or Erase Algorithm
cycle, successive attempts to read (OE toggling) data
from the device will result in DQ6 toggling between
one and zero. Once the Embedded Program or Erase
Algorithm cycle is completed, DQ6 will stop toggling
and valid data will be read on the next successive
attempts. During programming, the Toggle Bit is valid
after the rising edge of the fourth WE pulse in the four
write pulse sequence. For chip erase, the Toggle Bit
is valid after the rising edge of the sixth WE pulse in
the six write pulse sequence. For Sector erase, the
Toggle Bit is valid after the last rising edge of the
sector erase WE pulse. The Toggle Bit is active during
the sector time out.
In programming, if the sector being written to is pro-
tected, the toggle bit will toggle for about 2 s and then
stop toggling without the data having changed. In
erase, the device will erase all the selected sectors ex-
cept for the ones that are protected. If all selected sec-
tors are protected, the chip will toggle the toggle bit for
about 100 s and then drop back into read mode, hav-
ing changed none of the data.
Either CE or OE toggling will cause the DQ6 to toggle.
See Figure 13 for the Toggle Bit timing specifications
and diagrams.
DQ5
Exceeded Timing Limits
DQ5 will indicate if the program or erase time has ex-
ceeded the specified limits (internal pulse count).
Under these conditions DQ5 will produce a “1”. This is
a failure condition which indicates that the program or
erase cycle was not successfully completed. Data Poll-
ing is the only operating function of the device under
this condition. The CE circuit will partially power down
the device under these conditions (to approximately
2 mA). The OE and WE pins will control the output
disable functions as described in Table 1.
If this failure condition occurs during sector erase oper-
ation, it specifies that a particular sector is bad and it
may not be reused, however, other sectors are still
functional and may be used for the program or erase
operation. The device must be reset to use other sec-
tors. Write the Reset command sequence to the device,
and then execute program or erase command se-
quence. This allows the system to continue to use the
other active sectors in the device.
12
Am29F040
If this failure condition occurs during the chip erase op-
eration, it specifies that the entire chip is bad or combi-
nation of sectors are bad.
If this failure condition occurs during the byte program-
ming operation, it specifies that the entire sector con-
taining that byte is bad and this sector may not be
reused, (other sectors are still functional and can be
reused).
The DQ5 failure condition may also appear if a user
tries to program a “1” to a location previously pro-
grammed to “0”. In this case the device locks out and
never completes the Embedded Algorithm operation.
Hence, the system never reads a valid data on DQ7 bit
and DQ6 never stops toggling. Once the device has ex-
ceeded timing limits, the DQ5 bit will indicate a “1”.
Please note that this is not a device failure condition
since the device was incorrectly used.
DQ3
Sector Erase Timer
After the completion of the initial sector erase com-
mand sequence the sector erase time-out will begin.
DQ3 will remain low until the time-out is complete. Data
Polling and Toggle Bit are valid after the initial sector
erase command sequence.
If Data Polling or the Toggle Bit indicates the device has
been written with a valid erase command, DQ3 may be
used to determine if the sector erase timer window is
still open. If DQ3 is high (“1”) the internally controlled
erase cycle has begun; attempts to write subsequent
commands to the device will be ignored until the erase
operation is completed as indicated by Data Polling or
Toggle Bit. If DQ3 is low (“0”), the device will accept ad-
ditional sector erase commands. To insure the com-
mand has been accepted, the system software should
check the status of DQ3 prior to and following each
subsequent sector erase command. If DQ3 is high on
the second status check, the command may not have
been accepted.
Refer to Table 5, Write Operation Status.
Data Protection
The Am29F040 is designed to offer protection
against accidental erasure or programming caused
by spurious system level signals that may exist dur-
ing power transitions. During power up the device
automatically resets the internal state machine in the
Read mode. Also, with its control register architec-
ture, alteration of the memory contents only occurs
after successful completion of specific multi-bus
cycle command sequences.
The device also incorporates several features to
prevent inadvertent write cycles resulting from V
power-up and power-down transitions or system noise.
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