LH5116HD-10 Sharp Electronics, LH5116HD-10 Datasheet - Page 6

• Manufacturer Part Number: LH5116HD-10
• Manufacturer: Sharp Electronics

Specifications of LH5116HD-10

• Density: 16Kb
• Access Time (max): 100ns
• Sync/async: Asynchronous
• Architecture: Not Required
• Clock Freq (max): Not RequiredMHz
• Operating Supply Voltage (typ): 5V
• Address Bus: 11b
• Package Type: SDIP
• Operating Temp Range: -40C to 85C
• Number Of Ports: 1
• Supply Current: 40mA
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Operating Temperature Classification: Industrial
• Mounting: Through Hole
• Pin Count: 24
• Word Size: 8b
• Number Of Words: 2K
• Lead Free Status / Rohs Status: Not Compliant

LH5116/H
6
NOTES:
NOTES:
1. WE must be HIGH when there is a change in A
2. When CE and WE are both LOW at the same time, write occurs during the period t
3. t
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
5. D
6. If CE is LOW during this period, the input/output pins are in the output state. During this state, input
1. WE must be HIGH when there is a change in A
2. When CE and WE are both LOW at the same time, write occurs during the period t
3. t
4. If CE LOW transition occurs at the same time or after WE LOW transition, the outputs will remain high-impedance.
5. D
6. If CE is LOW during this period, the input/output pin is in the output state. During this state, input
signals of opposite logic level must not be applied.
WR
signals of opposite logic level must not be applied.
WR
OUT
OUT
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
A
is the time from the rise of CE or WE, whichever is first, to the end of the write cycle.
0
outputs data with the same logic level as the input data of this write cycle.
outputs data with the same logic level as the input data of this write cycle.
D
- A
OUT
OE
WE
CE
D
10
IN
OE = 'LOW'
A
0
D
- A
WE
OUT
CE
D
10
(NOTE 4)
IN
t
OHZ
t
AS
(NOTE 4)
t
AS
Figure 6. Write Cycle 2
Figure 5. Write Cycle 1
0
0
- A
t
- A
WHZ
10
10
.
.
t
t
CW
CW
t
AW
t
AW
(NOTE 2)
(NOTE 2)
t
WC
t
t
WC
t
WP
WP
t
DW
WP
WP
t
DW
.
.
t
WR
t
DH
(NOTE 3)
(NOTE 6)
(NOTE 3)
(NOTE 5)
(NOTE 6)
t
t
WR
OW
(NOTE 5)
t
DH
t
OW
CMOS 16K (2K
t
OLZ
8) Static RAM
5116-5
5116-4