VIPER20 STMicroelectronics, VIPER20 Datasheet - Page 14

• Manufacturer Part Number: VIPER20
• Manufacturer: STMicroelectronics

Specifications of VIPER20

• Pwm Type: Current Mode PWM Controller
• Number Of Pwm Outputs: 1
• On/off Pin: No
• Adjustable Output: No
• Switching Freq: 200kHz
• Operating Supply Voltage (max): 15V
• Output Current: 500mA
• Output Voltage: 620V
• Synchronous Pin: No
• Rise Time: 50ns
• Fall Time: 100ns
• Mounting: Through Hole
• Pin Count: 5 +Tab
• Package Type: PENTAWATT HV
• Lead Free Status / Rohs Status: Not Compliant

TRANSCONDUCTANCE ERROR AMPLIFIER
The VIPer20/20A includes a transconductance
error amplifier. Transconductance Gm is the
change in output current (I
input voltage (V
G
The output impedance Z
amplifier (COMP pin) can be defined as:
This last equation shows that the open loop gain
A
A
where G
typically.
G
therefore A
impedance Z can be connected between the
COMP pin and ground in order to define more
accurately the transfer function F of the error
amplifier, according to the following equation, very
similar to the one above:
F
The error amplifier frequency response is reported
in figure 10 for different values of a simple
resistance connected on the COMP pin. The
unloaded transconductance error amplifier shows
an internal Z
impedance can be connected on the COMP pin to
Figure 16: Mixed Soft Start and Compensation
Z COMP
(S)
VOL
VOL
m
m
+ C3
is well defined by specification, but Z
= Gm x Z(S)
=
can be related to G
= G
OS C
----------------------- -
I COMP
m
m
1 3V
V DD
=
VD D
VOL
x Z
value for VIPer50/50A is 1.5 mA/V
COMP
-------------------------- -
C 4
+
-
V COMP
I COM P
COMP
are subject to large tolerances. An
DD
VIPer20
COMP
). Thus:
of about 330 K . More complex
C 1
S OU RCE
R 1
DRAIN
=
COMP
m
COMP
-------- -
G
and Z
1
D 1
m
+ C2
at the output of this
) versus change in
-------------------------- -
COMP
FC00431
V COM P
R 3
R 2
V
D 2
D 3
DD
:
COMP
AU XI LIARY
WI N DIN G
and
achieve different compensation laws. A capacitor
will provide an integrator function, thus eliminating
the DC static error, and a resistance in series
leads to a flat gain at higher frequency, insuring a
correct phase margin. This configuration is
illustrated in figure 18.
As shown in figure 18 an additional noise filtering
capacitor of 2.2 nF is generally needed to avoid
any high frequency interference.
It can also be interesting to implement a slope
compensation when working in continuous mode
with duty cycle higher than 50%. Figure 19 shows
such a configuration. Note that R1 and C2 build
the classical compensation network, and Q1 is
injecting the slope compensation with the correct
polarity from the oscillator sawtooth.
EXTERNAL CLOCK SYNCHRONIZATION
The
capability, when connected to an external
frequency source. Figure 20 shows one possible
schematic to be adapted depending on the
specific needs. If the proposed schematic is used,
the pulse duration must be kept at a low value
(500ns is sufficient) for minimizing consumption.
The optocoupler must be able to provide 20mA
through the optotransistor.
PRIMARY PEAK CURRENT LIMITATION
The primary I
effect, the output power can be limited using the
simple circuit shown in figure 21. The circuit based
on Q1, R
Figure 17: Latched Shut Down
Shutdown
VIPer20/SP/DIP - VIPer20A/ASP/ADIP
OSC
1
and R
R4
pin
DPEAK
Q2
R3
provides
2
clamps the voltage on the
current and, as resulting
Q1
R1
R2
OSC
a
13V
VDD
D1
synchronisation
+
-
VIPer20
FC00440
COMP SOURCE
DRAIN
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