LH28F008SCT-V85 Sharp Electronics, LH28F008SCT-V85 Datasheet - Page 6

• Manufacturer Part Number: LH28F008SCT-V85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCT-V85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

to read data from, or write data to any other flash
memory array location.
Individual block locking uses a combination of bits,
sixteen block lock-bits and a master lock-bit, to lock
and unlock blocks. Block lock-bits gate block erase
and byte write operations, while the master lock-bit
gates
configuration operations (Set Block Lock-Bit, Set
Master Lock-Bit, and Clear Block Lock-Bits
commands) set and cleared lock-bits.
The status register indicates when the WSM ’ s block
erase, byte write, or lock-bit configuration operation
is finished.
The RY/BY# output gives an additional indicator of
WSM activity by providing both a hardware signal
of status (versus software polling) and status
masking (interrupt masking for background block
erase, for example). Status polling using RY/BY#
minimizes both CPU overhead and system power
consumption. When low, RY/BY# indicates that the
WSM is performing a block erase, byte write, or
lock-bit configuration. RY/BY#-high indicates that
the WSM is ready for a new command, block erase
is suspended (and byte write is inactive), byte write
is suspended, or the device is in deep power-down
mode.
The access time is 85 ns (t
voltage range of 4.75 to 5.25 V over the
temperature range, 0 to +70˚C (LH28F008SC-V)/
–25 to +85˚C (LH28F008SCH-V). At 4.5 to 5.5 V
V
The Automatic Power Saving (APS) feature
substantially reduces active current when the
device is in static mode (addresses not switching).
In APS mode, the typical I
5 V V
CC
, the access time is 90 ns or 120 ns.
CC
.
block
lock-bit
modification.
AVQV
CCR
) at the V
current is 1 mA at
CC
Lock-bit
supply
- 6 -
When CE# and RP# pins are at V
CMOS standby mode is enabled. When the RP#
pin is at GND, deep power-down mode is enabled
which minimizes power consumption and provides
write protection during reset. A reset time (t
required from RP# switching high until outputs are
valid. Likewise, the device has a wake time (t
from RP#-high until writes to the CUI are
recognized. With RP# at GND, the WSM is reset
and the status register is cleared.
FFFFF
F0000
EFFFF
E0000
DFFFF
D0000
CFFFF
C0000
BFFFF
B0000
AFFFF
A0000
9FFFF
90000
8FFFF
80000
7FFFF
70000
6FFFF
60000
5FFFF
50000
4FFFF
40000
3FFFF
30000
2FFFF
20000
1FFFF
10000
0FFFF
00000
Fig. 1 Memory Map
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
64 k-Byte Block
LH28F008SC-V/SCH-V
CC
, the I
PHQV
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PHEL
) is
CC
)