LH28F008SCR-V12 Sharp Electronics, LH28F008SCR-V12 Datasheet - Page 21

• Manufacturer Part Number: LH28F008SCR-V12
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCR-V12

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 120ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP-I
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

FULL STATUS CHECK PROCEDURE
Block/Device Address
Block/Device Address
Read Status Register
Data (See Above)
Check if Desired
Write 01H/F1H,
Status Register
Set Lock-Bit
Set Lock-Bit
Write 60H,
Full Status
Successful
Complete
SR.4, 5 =
SR.7 =
SR.3 =
SR.1 =
SR.4 =
Read
Start
0
0
0
0
1
0
1
1
1
1
Fig. 7 Set Block and Master Lock-Bit Flowchart
Command Sequence
Device Protect Error
V
PP
Set Lock-Bit
Range Error
Error
Error
OPERATION COMMAND
Standby
Standby
Standby
Standby
- 21 -
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear
Status Register command in cases where multiple lock-bits are
set before full status is checked.
If error is detected, clear the status register before attempting
retry or other error recovery.
OPERATION
Write
Write
Read
Standby
BUS
Repeat for subsequent lock-bit set operations.
Full status check can be done after each lock-bit set
operation or after a sequence of lock-bit set operations.
Write FFH after the last lock-bit set operation to place device
in read array mode.
BUS
Block or Master
Block/Master
COMMAND
Lock-Bit
Lock-Bit
Confirm
Setup
Set
Set
Check SR.3
1 = V
Check SR.4, 5
Both 1 = Command Sequence Error
Check SR.1
1 = Device Protect Detect
RP# = V
RP# = V
Check SR.4
1 = Set Lock-Bit Error
(Set Master Lock-Bit Operation)
(Set Block Lock-Bit Operation)
PP
Data = 60H
Addr = Block Address (Block),
Data = 01H (Block),
Addr = Block Address (Block),
Status Register Data
Check SR.7
1 = WSM Ready
0 = WSM Busy
Error Detect
IH
IH
, Master Lock-Bit is Set
COMMENTS
Device Address (Master)
F1H (Master)
Device Address (Master)
COMMENTS
LH28F008SC-V/SCH-V