LH28F008BVT-BTL10 Sharp Electronics, LH28F008BVT-BTL10 Datasheet - Page 14

• Manufacturer Part Number: LH28F008BVT-BTL10
• Manufacturer: Sharp Electronics

Specifications of LH28F008BVT-BTL10

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 100ns
• Interface Type: Parallel
• Boot Type: Bottom
• Address Bus: 20b
• Operating Supply Voltage (typ): 3.3V
• Operating Temp Range: 0C to 70C
• Package Type: TSOP
• Program/erase Volt (typ): 3.3/5/12V
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 2.7V
• Operating Supply Voltage (max): 3.6V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 30mA
• Mounting: Surface Mount
• Pin Count: 40
• Lead Free Status / Rohs Status: Not Compliant

4.8 Byte Write Suspend Command
The Byte Write Suspend command allows byte write
interruption to read data in other flash memory locations.
Once the byte write process starts, writing the Byte Write
Suspend command requests that the WSM suspend the
byte write sequence at a predetermined point in the
algorithm. The device continues to output status register
data when read after the Byte Write Suspend command is
written. Polling status register bits SR.7 and SR.2 can
determine when the byte write operation has been
suspended (both will be set to "1"). Specification section
6.2.8 defines the byte write suspend latency.
At this point, a Read Array command can be written to
read data from locations other than that which is
suspended. The only other valid commands while byte
write is suspended are Read Status Register and Byte
Write Resume. After Byte Write Resume command is
written to the flash memory, the WSM will continue the
byte write process. Status register bits SR.2 and SR.7 will
automatically clear. After the Byte Write Resume
command is written, the device automatically outputs
status register data when read (see Figure 8). V
remain at V
write) while in byte write suspend mode. RP# must also
remain at V
write). WP# must also remain at V
WP# level used for byte write).
4.9 Considerations of Suspend
After the suspend command write to the CUI, read status
register command has to write to CUI, then status register
bit SR.6 or SR.2 should be checked for places the device
in suspend mode.
Block Erase
Byte Write
Operation
or
IH
PPH1/2/3
or V
HH
(the same V
(the same RP# level used for byte
>V
V
V
PPLK
PP
IL
PP
IL
V
RP#
V
level used for byte
V
X
HH
IH
IL
or V
Table 6. Write Protection Alternatives
IH
(the same
PP
WP#
V
V
X
X
X
IH
IL
must
All Blocks Locked.
All Blocks Locked.
All Blocks Unlocked.
2 Boot Blocks Locked.
All Blocks Unlocked.
4.10 Block Locking
This Boot Block Flash memory architecture features two
hardware-lockable boot blocks so that the kernel code for
the system can be kept secure while other blocks are
programmed or erased as necessary.
4.10.1 V
The V
complete write protection of all blocks in the flash device.
4.10.2 WP#=V
The lockable blocks are locked when WP#=V
program or erase operation to a locked block will result in
an error, which will be reflected in the status register. For
top configuration, the top two boot blocks are lockable.
For the bottom configuration, the bottom two boot blocks
are lockable. Unlocked blocks can be programmed or
erased normally (Unless V
4.10.3 WP#=V
WP#=V
These blocks can now be programmed or erased.
WP# controls 2 boot blocks locking and V
protection against spurious writes. Table 6 defines the
write protection methods.
PP
IH
unlocks all lockable blocks.
programming voltage can be held low for
PP
=V
IL
IL
IH
for Complete Protection
for Block Locking
Effect
for Block Unlocking
PP
is below V
PPLK
).
PP
provides
Rev. 1.1
IL
; any