LH28F008SCN-V85 Sharp Electronics, LH28F008SCN-V85 Datasheet - Page 12

• Manufacturer Part Number: LH28F008SCN-V85
• Manufacturer: Sharp Electronics

Specifications of LH28F008SCN-V85

• Cell Type: NOR
• Density: 8Mb
• Access Time (max): 85ns
• Interface Type: Parallel
• Boot Type: Not Required
• Address Bus: 20b
• Operating Supply Voltage (typ): 5V
• Operating Temp Range: 0C to 70C
• Package Type: SOP
• Sync/async: Asynchronous
• Operating Temperature Classification: Commercial
• Operating Supply Voltage (min): 4.5V
• Operating Supply Voltage (max): 5.5V
• Word Size: 8b
• Number Of Words: 1M
• Supply Current: 50mA
• Mounting: Surface Mount
• Pin Count: 44
• Lead Free Status / Rohs Status: Not Compliant

4.1 Read Array Command
Upon initial device power-up and after exit from
deep power-down mode, the device defaults to
read array mode. This operation is also initiated by
writing the Read Array command. The device
remains enabled for reads until another command
is written. Once the internal WSM has started a
block erase, byte write or lock-bit configuration, the
device will not recognize the Read Array command
until the WSM completes its operation unless the
WSM is suspended via an Erase Suspend or Byte
Write Suspend command. The Read Array
command functions independently of the V
voltage and RP# can be V
4.2 Read Identifier Codes Command
The identifier code operation is initiated by writing
the Read Identifier Codes command. Following the
command write, read cycles from addresses shown
in Fig. 2 retrieve the manufacture, device, block
lock configuration and master lock configuration
codes (see Table 4 for identifier code values). To
terminate the operation, write another valid
command. Like the Read Array command, the
Read
independently of the V
V
command, the following information can be read :
NOTE :
1. X selects the specific block lock configuration code to be
Manufacture Code
Device Code
Block Lock Configuration
• Block is Unlocked
• Block is Locked
• Reserved for Future Use
Master Lock Configuration
• Device is Unlocked
• Device is Locked
• Reserved for Future Use
IH
read. See Fig. 2 for the device identifier code memory
map.
or V
Identifier
HH
. Following the Read Identifier Codes
CODE
Table 4 Identifier Codes
Codes
PP
voltage and RP# can be
IH
or V
command
X0002H
ADDRESS
00000H
00001H
00003H
HH
.
(NOTE 1)
functions
DQ
DQ
DQ
DQ
DQ
DQ
DATA
A6
89
0
0
0
0
1-7
1-7
= 0
= 1
= 0
= 1
PP
- 12 -
4.3 Read Status Register Command
The status register may be read to determine when
a block erase, byte write, or lock-bit configuration is
complete and whether the operation completed
successfully. It may be read at any time by writing
the Read Status Register command. After writing
this command, all subsequent read operations
output data from the status register until another
valid command is written. The status register
contents are latched on the falling edge of OE# or
CE#, whichever occurs. OE# or CE# must toggle to
V
register latch. The Read Status Register command
functions independently of the V
can be V
4.4 Clear Status Register Command
Status register bits SR.5, SR.4, SR.3, and SR.1 are
set to "1"s by the WSM and can only be reset by
the Clear Status Register command. These bits
indicate various failure conditions (see Table 6). By
allowing system software to reset these bits,
several operations (such as cumulatively erasing or
locking multiple blocks or writing several bytes in
sequence) may be performed. The status register
may be polled to determine if an error occurred
during the sequence.
To clear the status register, the Clear Status
Register command (50H) is written. It functions
independently of the applied V
be V
during block erase or byte write suspend modes.
4.5 Block Erase Command
Erase is executed one block at a time and initiated
by a two-cycle command. A block erase setup is
first written, followed by a block erase confirm.
This command sequence requires appropriate
sequencing and an address within the block to be
erased (erase changes all block data to FFH).
Block preconditioning, erase, and verify are handled
internally by the WSM (invisible to the system).
After the two-cycle block erase sequence is written,
IH
before further reads to update the status
IH
or V
IH
or V
HH
. This command is not functional
HH
.
LH28F008SC-V/SCH-V
PP
voltage. RP# can
PP
voltage. RP#